Design method to transmit and receive source synchronous signals using source asynchronous

Field Programmable Gate Array (FPGA) yang berkos rendah menawarkan data dengan kelajuan terhad untuk saluran sumber segerak Low-Voltage Differential Signaling (LVDS) Input-Output (IO) tetapi kelajuan lebih tinggi untuk saluran sumber tidak segerak. Cyclone V adalah peranti berkos rendah yang menawar...

Full description

Saved in:

Bibliographic Details
Main Author:	Ramachandran, Nathan
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design
Online Access:	http://eprints.usm.my/33021/1/NATHAN_RAMACHANDRAN_DESIGN_METHOD_TO_TRANSMIT_AND_RECEIVE_SOURCE_SYNCHRONOUS_SIGNALS_USING_SOURCE_ASYNCHRONOUS_TRANSCEIVER_CHANNELS_2013_MA_E%26E_BSB_24.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-usm-ep.33021
record_format	uketd_dc
spelling	my-usm-ep.330212019-04-12T05:26:19Z Design method to transmit and receive source synchronous signals using source asynchronous 2013 Ramachandran, Nathan TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design Field Programmable Gate Array (FPGA) yang berkos rendah menawarkan data dengan kelajuan terhad untuk saluran sumber segerak Low-Voltage Differential Signaling (LVDS) Input-Output (IO) tetapi kelajuan lebih tinggi untuk saluran sumber tidak segerak. Cyclone V adalah peranti berkos rendah yang menawarkan saluran LVDS IO yang menyokong kadar kelajuan 1.25 Gigabit sesaat (Gbps) tetapi saluran tidak segeraknya menyokong kadar kelajuan 5 Gbps. Secara umum, satu lagi had sumber sistem segerak adalah jarak penghantaran saluran jam perlu sependek yang mungkin untuk menghapuskan condong antara saluran data dan saluran jam. Maka, objektif kajian ini adalah membentangkan penyelesaian untuk menghantar dan menerima sumber isyarat segerak pada kelajuan yang lebih tinggi menggunakan saluran sumber tidak segerak yang terdapat dalam peranti FPGA. Penyelesaian yang dicadangkan juga akan membolehkan jarak penghantaran saluran jam yang lebih panjang digunakan. Lower cost Field Programmable Gate Array (FPGA) devices offer limited data rate speed for source synchronous Low-Voltage Differential Signaling (LVDS) Input-Output (IO) interfaces but higher data rate speeds for source asynchronous transceivers channels. Cyclone V which is a low cost FPGA device supports LVDS IO channels for data rates up-till 1.25 Gigabit per second (Gbps) meanwhile the transceiver channels support data rates up-till 5 Gbps. In general, another known limitation of source synchronous system is the clock transmission path need to be as short as possible to eliminate high skew between data channel and clock channel. Hence, this research objective is to presents a solution to transmit and receive source synchronous signals at higher data rates using the available source asynchronous channels in the FPGA devices. The solution will also address the limitation of clock transmission path length. 2013 Thesis http://eprints.usm.my/33021/ http://eprints.usm.my/33021/1/NATHAN_RAMACHANDRAN_DESIGN_METHOD_TO_TRANSMIT_AND_RECEIVE_SOURCE_SYNCHRONOUS_SIGNALS_USING_SOURCE_ASYNCHRONOUS_TRANSCEIVER_CHANNELS_2013_MA_E%26E_BSB_24.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design
spellingShingle	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design Ramachandran, Nathan Design method to transmit and receive source synchronous signals using source asynchronous
description	Field Programmable Gate Array (FPGA) yang berkos rendah menawarkan data dengan kelajuan terhad untuk saluran sumber segerak Low-Voltage Differential Signaling (LVDS) Input-Output (IO) tetapi kelajuan lebih tinggi untuk saluran sumber tidak segerak. Cyclone V adalah peranti berkos rendah yang menawarkan saluran LVDS IO yang menyokong kadar kelajuan 1.25 Gigabit sesaat (Gbps) tetapi saluran tidak segeraknya menyokong kadar kelajuan 5 Gbps. Secara umum, satu lagi had sumber sistem segerak adalah jarak penghantaran saluran jam perlu sependek yang mungkin untuk menghapuskan condong antara saluran data dan saluran jam. Maka, objektif kajian ini adalah membentangkan penyelesaian untuk menghantar dan menerima sumber isyarat segerak pada kelajuan yang lebih tinggi menggunakan saluran sumber tidak segerak yang terdapat dalam peranti FPGA. Penyelesaian yang dicadangkan juga akan membolehkan jarak penghantaran saluran jam yang lebih panjang digunakan. Lower cost Field Programmable Gate Array (FPGA) devices offer limited data rate speed for source synchronous Low-Voltage Differential Signaling (LVDS) Input-Output (IO) interfaces but higher data rate speeds for source asynchronous transceivers channels. Cyclone V which is a low cost FPGA device supports LVDS IO channels for data rates up-till 1.25 Gigabit per second (Gbps) meanwhile the transceiver channels support data rates up-till 5 Gbps. In general, another known limitation of source synchronous system is the clock transmission path need to be as short as possible to eliminate high skew between data channel and clock channel. Hence, this research objective is to presents a solution to transmit and receive source synchronous signals at higher data rates using the available source asynchronous channels in the FPGA devices. The solution will also address the limitation of clock transmission path length.
format	Thesis
qualification_level	Master's degree
author	Ramachandran, Nathan
author_facet	Ramachandran, Nathan
author_sort	Ramachandran, Nathan
title	Design method to transmit and receive source synchronous signals using source asynchronous
title_short	Design method to transmit and receive source synchronous signals using source asynchronous
title_full	Design method to transmit and receive source synchronous signals using source asynchronous
title_fullStr	Design method to transmit and receive source synchronous signals using source asynchronous
title_full_unstemmed	Design method to transmit and receive source synchronous signals using source asynchronous
title_sort	design method to transmit and receive source synchronous signals using source asynchronous
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik & Elektronik
publishDate	2013
url	http://eprints.usm.my/33021/1/NATHAN_RAMACHANDRAN_DESIGN_METHOD_TO_TRANSMIT_AND_RECEIVE_SOURCE_SYNCHRONOUS_SIGNALS_USING_SOURCE_ASYNCHRONOUS_TRANSCEIVER_CHANNELS_2013_MA_E%26E_BSB_24.pdf
_version_	1747820577773584384

Design method to transmit and receive source synchronous signals using source asynchronous

Similar Items