Agnostic Validation Test Bench For Efuse Connectivity Verification

In semiconductor industry, validation is an important process to discover design bugs and have it fixed before the product is released. Semiconductor integrated circuit is normally refreshed in yearly cadence and it is crucial to have a short design and validation cycle, without compromising the pro...

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Main Author:	CHAN , WEI JIAN
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/38350/1/CHAN_WEI_JIAN_24_Pages.pdf
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id	my-usm-ep.38350
record_format	uketd_dc
spelling	my-usm-ep.383502020-10-08T03:23:16Z Agnostic Validation Test Bench For Efuse Connectivity Verification 2017 CHAN , WEI JIAN TK1-9971 Electrical engineering. Electronics. Nuclear engineering In semiconductor industry, validation is an important process to discover design bugs and have it fixed before the product is released. Semiconductor integrated circuit is normally refreshed in yearly cadence and it is crucial to have a short design and validation cycle, without compromising the product quality. Nowadays, validation process often becomes the bottleneck for product readiness. Integrated circuit validation flow has to be improved in order to keep up with the advancement of integrated circuit design flow. In this work, an improvement method on validation flow is discussed, with particular focus on eFUSE (Electric FUSE) connectivity validation. eFUSE is a feature available in integrated circuit which functions as a central storage for important ‘settings’, and distribute them during system boot up process. eFUSE connectivity validation is needed to ensure each intellectual property is able to retrieve the correct eFUSE value. In this work, the concept of agnostic validation test bench for eFUSE connectivity validation is developed and tested the idea of it is to eliminate manual test development effort, improves validation efficiency and promotes reusability across different projects. By using this methodology, eFUSE connectivity validation time is reduced significantly and recorded an improvement of 28%. There is also an average improvement of 65% in eFUSE coverage percentage. In summary, the eFUSE connectivity validation time frame is shortened, without compromising the test quality. 2017 Thesis http://eprints.usm.my/38350/ http://eprints.usm.my/38350/1/CHAN_WEI_JIAN_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering CHAN , WEI JIAN Agnostic Validation Test Bench For Efuse Connectivity Verification
description	In semiconductor industry, validation is an important process to discover design bugs and have it fixed before the product is released. Semiconductor integrated circuit is normally refreshed in yearly cadence and it is crucial to have a short design and validation cycle, without compromising the product quality. Nowadays, validation process often becomes the bottleneck for product readiness. Integrated circuit validation flow has to be improved in order to keep up with the advancement of integrated circuit design flow. In this work, an improvement method on validation flow is discussed, with particular focus on eFUSE (Electric FUSE) connectivity validation. eFUSE is a feature available in integrated circuit which functions as a central storage for important ‘settings’, and distribute them during system boot up process. eFUSE connectivity validation is needed to ensure each intellectual property is able to retrieve the correct eFUSE value. In this work, the concept of agnostic validation test bench for eFUSE connectivity validation is developed and tested the idea of it is to eliminate manual test development effort, improves validation efficiency and promotes reusability across different projects. By using this methodology, eFUSE connectivity validation time is reduced significantly and recorded an improvement of 28%. There is also an average improvement of 65% in eFUSE coverage percentage. In summary, the eFUSE connectivity validation time frame is shortened, without compromising the test quality.
format	Thesis
qualification_level	Master's degree
author	CHAN , WEI JIAN
author_facet	CHAN , WEI JIAN
author_sort	CHAN , WEI JIAN
title	Agnostic Validation Test Bench For Efuse Connectivity Verification
title_short	Agnostic Validation Test Bench For Efuse Connectivity Verification
title_full	Agnostic Validation Test Bench For Efuse Connectivity Verification
title_fullStr	Agnostic Validation Test Bench For Efuse Connectivity Verification
title_full_unstemmed	Agnostic Validation Test Bench For Efuse Connectivity Verification
title_sort	agnostic validation test bench for efuse connectivity verification
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/38350/1/CHAN_WEI_JIAN_24_Pages.pdf
_version_	1747820687105458176

Agnostic Validation Test Bench For Efuse Connectivity Verification

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