A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
The Bluetooth™ standards is one of the major driving forces of the short-range wireless communications market as well as home and office environments. There are many Bluetooth™ standards covering the signal bandwidth from 500 KHz to 25 MHz. For low frequency data sampling, SAR and Delta-Sigma ADC ar...
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2017
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| 主題: | |
| 在線閱讀: | http://eprints.usm.my/39410/1/KHOO_BOON_HEE_24_Pages.pdf |
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| 總結: | The Bluetooth™ standards is one of the major driving forces of the short-range wireless communications market as well as home and office environments. There are many Bluetooth™ standards covering the signal bandwidth from 500 KHz to 25 MHz. For low frequency data sampling, SAR and Delta-Sigma ADC are preferred architecture for signal bandwidth of below 3 MHz and pipelined ADC is prefer for 5 MHz and above. This research is to deploy pipelined ADC as single architecture that able to cover Bluetooth™ standard from BT1.1 to BT4.0. The targeted sampling rate is 100MS/s with 10 bit resolution at 1.8V power and designed using Silterra CMOS 0.18um process. Flipped Voltage Follower (FVF) operational amplifier has been recommended as operational amplifier to achieve high sampling rate .Ten stages pipelined ADC was developed and tested at 50MS/s and 100MS/s. The sampling rate has achieved by measureable of 50MS/s and the power consumption is 54mW. Sampling rate can be increased further by improving the gain bandwidth of the FVF Op-Amp through the implementation of the digital calibration and common mode feedback (CMFB) circuit. |
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