A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology

The Bluetooth™ standards is one of the major driving forces of the short-range wireless communications market as well as home and office environments. There are many Bluetooth™ standards covering the signal bandwidth from 500 KHz to 25 MHz. For low frequency data sampling, SAR and Delta-Sigma ADC ar...

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التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Khoo , Boon Hee
التنسيق:	أطروحة
اللغة:	English
منشور في:	2017
الموضوعات:	TK1-9971 Electrical engineering Electronics Nuclear engineering
الوصول للمادة أونلاين:	http://eprints.usm.my/39410/1/KHOO_BOON_HEE_24_Pages.pdf
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

id	my-usm-ep.39410
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spelling	my-usm-ep.394102019-04-12T05:25:06Z A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology 2017 Khoo , Boon Hee TK1-9971 Electrical engineering. Electronics. Nuclear engineering The Bluetooth™ standards is one of the major driving forces of the short-range wireless communications market as well as home and office environments. There are many Bluetooth™ standards covering the signal bandwidth from 500 KHz to 25 MHz. For low frequency data sampling, SAR and Delta-Sigma ADC are preferred architecture for signal bandwidth of below 3 MHz and pipelined ADC is prefer for 5 MHz and above. This research is to deploy pipelined ADC as single architecture that able to cover Bluetooth™ standard from BT1.1 to BT4.0. The targeted sampling rate is 100MS/s with 10 bit resolution at 1.8V power and designed using Silterra CMOS 0.18um process. Flipped Voltage Follower (FVF) operational amplifier has been recommended as operational amplifier to achieve high sampling rate .Ten stages pipelined ADC was developed and tested at 50MS/s and 100MS/s. The sampling rate has achieved by measureable of 50MS/s and the power consumption is 54mW. Sampling rate can be increased further by improving the gain bandwidth of the FVF Op-Amp through the implementation of the digital calibration and common mode feedback (CMFB) circuit. 2017 Thesis http://eprints.usm.my/39410/ http://eprints.usm.my/39410/1/KHOO_BOON_HEE_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Khoo , Boon Hee A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
description	The Bluetooth™ standards is one of the major driving forces of the short-range wireless communications market as well as home and office environments. There are many Bluetooth™ standards covering the signal bandwidth from 500 KHz to 25 MHz. For low frequency data sampling, SAR and Delta-Sigma ADC are preferred architecture for signal bandwidth of below 3 MHz and pipelined ADC is prefer for 5 MHz and above. This research is to deploy pipelined ADC as single architecture that able to cover Bluetooth™ standard from BT1.1 to BT4.0. The targeted sampling rate is 100MS/s with 10 bit resolution at 1.8V power and designed using Silterra CMOS 0.18um process. Flipped Voltage Follower (FVF) operational amplifier has been recommended as operational amplifier to achieve high sampling rate .Ten stages pipelined ADC was developed and tested at 50MS/s and 100MS/s. The sampling rate has achieved by measureable of 50MS/s and the power consumption is 54mW. Sampling rate can be increased further by improving the gain bandwidth of the FVF Op-Amp through the implementation of the digital calibration and common mode feedback (CMFB) circuit.
format	Thesis
qualification_level	Master's degree
author	Khoo , Boon Hee
author_facet	Khoo , Boon Hee
author_sort	Khoo , Boon Hee
title	A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
title_short	A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
title_full	A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
title_fullStr	A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
title_full_unstemmed	A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology
title_sort	1.8v 10-bit 100ms/s fully differential pipelined adc in cmos 0.18um process technology
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/39410/1/KHOO_BOON_HEE_24_Pages.pdf
_version_	1747820749596393472

A 1.8v 10-Bit 100ms/S Fully Differential Pipelined Adc In Cmos 0.18um Process Technology

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