Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses

Image compression is of great importance in multimedia systems and applications because it drastically reduces bandwidth requirements for transmission and memory requirements for storage. An image compression algorithm JPEG2000 isbased on Discrete Wavelet Transform. In the hardware implementation o...

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Main Author:	Ahmed Saad, Laila
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/39413/1/Laila_Ahmed_Saad_24_Pages.pdf
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id	my-usm-ep.39413
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spelling	my-usm-ep.394132019-04-12T05:25:05Z Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses 2017 Ahmed Saad, Laila TK1-9971 Electrical engineering. Electronics. Nuclear engineering Image compression is of great importance in multimedia systems and applications because it drastically reduces bandwidth requirements for transmission and memory requirements for storage. An image compression algorithm JPEG2000 isbased on Discrete Wavelet Transform. In the hardware implementation of DiscreteWavelet Transform (DWT) and inverse DiscreteWavelet Transform (IDWT),the main problems are storage memory, internal processing buffer, and the limitation of the FPGA resources. Based on non-separable 2-D DWT, the method used to access the image memory has a direct impact on the internal buffer size,the power consumption and, the transformation speed. The need for internal buffer reduces the image memory access time. The main objectives of this thesis are as follows; to implement a 2-D Haar wavelet transform for large gray-scale image, to reduce the number of image memory access by implementing the 2- D Haar wavelet transform with a suitable combination between using external memory and internal memory, and targeting a low-power and high-speed architecture based on multi-levels non-separable discrete Haar wavelet transform. In this work, the proposed two architectures reduce the number of image memory access. The line-based architecture reduces the internal buffer by 2 x 0.5 x N where N presents the image size. This happens for the low-pass coefficients and for the high-pass coefficients. The dual-scan architecture does not use the internal memory. Overall both architectures work well on the Altera FPGA board at frequency 100 MHz. 2017 Thesis http://eprints.usm.my/39413/ http://eprints.usm.my/39413/1/Laila_Ahmed_Saad_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Ahmed Saad, Laila Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses
description	Image compression is of great importance in multimedia systems and applications because it drastically reduces bandwidth requirements for transmission and memory requirements for storage. An image compression algorithm JPEG2000 isbased on Discrete Wavelet Transform. In the hardware implementation of DiscreteWavelet Transform (DWT) and inverse DiscreteWavelet Transform (IDWT),the main problems are storage memory, internal processing buffer, and the limitation of the FPGA resources. Based on non-separable 2-D DWT, the method used to access the image memory has a direct impact on the internal buffer size,the power consumption and, the transformation speed. The need for internal buffer reduces the image memory access time. The main objectives of this thesis are as follows; to implement a 2-D Haar wavelet transform for large gray-scale image, to reduce the number of image memory access by implementing the 2- D Haar wavelet transform with a suitable combination between using external memory and internal memory, and targeting a low-power and high-speed architecture based on multi-levels non-separable discrete Haar wavelet transform. In this work, the proposed two architectures reduce the number of image memory access. The line-based architecture reduces the internal buffer by 2 x 0.5 x N where N presents the image size. This happens for the low-pass coefficients and for the high-pass coefficients. The dual-scan architecture does not use the internal memory. Overall both architectures work well on the Altera FPGA board at frequency 100 MHz.
format	Thesis
qualification_level	Master's degree
author	Ahmed Saad, Laila
author_facet	Ahmed Saad, Laila
author_sort	Ahmed Saad, Laila
title	Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses
title_short	Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses
title_full	Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses
title_fullStr	Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses
title_full_unstemmed	Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses
title_sort	efficient hardware implementation of haar wavelet transform with line-based and dual-scan image memory accesses
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/39413/1/Laila_Ahmed_Saad_24_Pages.pdf
_version_	1747820750330396672

Efficient Hardware Implementation Of Haar Wavelet Transform With Line-Based And Dual-Scan Image Memory Accesses

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