Power Management Controller By Using Intel Max 10 Fpga

Currently, FPGA (Field Programmable Gate Array) is one of the choices that consider for digital system design compare to ASIC (Application-Specific Integrated Circuit). This is due to the flexibility of the FPGA to update design based on the application. Intel Stratix 10 FPGA is the FPGA from Intel...

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Main Author:	Ooi , Kheng Jin
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/39565/1/OOI_KHENG_JIN_24_Pages.pdf
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id	my-usm-ep.39565
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spelling	my-usm-ep.395652019-04-12T05:25:07Z Power Management Controller By Using Intel Max 10 Fpga 2017 Ooi , Kheng Jin TK1-9971 Electrical engineering. Electronics. Nuclear engineering Currently, FPGA (Field Programmable Gate Array) is one of the choices that consider for digital system design compare to ASIC (Application-Specific Integrated Circuit). This is due to the flexibility of the FPGA to update design based on the application. Intel Stratix 10 FPGA is the FPGA from Intel Cooperation that required proper power sequencing to avoid damage on the devices. Besides power sequencing, Intel Stratix 10 FPGA required 200 us to 100 ms POR (Power On Reset) during power up sequence to avoid FPGA in reset state and require total power down sequence in 100 ms. There are a lot of power sequencing methods are implemented for FPGA such as discrete component, resistor divider rule, sequencing IC (Integrated Circuit), MCU (Microcontroller), CPLD (Complex Programmable Logic Device) and FPGA. All these approaches are used to control the power on and off for the voltage regulator through pin enable voltage regulator and standard interface such as SM (System Management) Bus and PM (Power Management) Bus. For this project, non-volatile Intel MAX 10 FPGA is used for power management controller. This FPGA include internal ADC (Analog to Digital Converter) and UFM (User Flash Memory) that is critical to design power management controller. Power management controller is running on NIOS II and Avalon-MM (Memory-Mapped) Bus is used to connect all the ADC, UFM, timer, UART (Universal Asynchronous Receiver/Transmitter), PWM (Pulse Width Modulation) and PM Bus. This project is to power up and power down the PM Bus compatible voltage regulator within the POR specification which is 200 us to 100 ms and achieve 100 ms power down for FPGA. There are a number of advantages using Intel MAX 10 FPGA such as built in ADC, UFM, flexibility of FPGA, and NIOS II soft processor. 2017 Thesis http://eprints.usm.my/39565/ http://eprints.usm.my/39565/1/OOI_KHENG_JIN_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Ooi , Kheng Jin Power Management Controller By Using Intel Max 10 Fpga
description	Currently, FPGA (Field Programmable Gate Array) is one of the choices that consider for digital system design compare to ASIC (Application-Specific Integrated Circuit). This is due to the flexibility of the FPGA to update design based on the application. Intel Stratix 10 FPGA is the FPGA from Intel Cooperation that required proper power sequencing to avoid damage on the devices. Besides power sequencing, Intel Stratix 10 FPGA required 200 us to 100 ms POR (Power On Reset) during power up sequence to avoid FPGA in reset state and require total power down sequence in 100 ms. There are a lot of power sequencing methods are implemented for FPGA such as discrete component, resistor divider rule, sequencing IC (Integrated Circuit), MCU (Microcontroller), CPLD (Complex Programmable Logic Device) and FPGA. All these approaches are used to control the power on and off for the voltage regulator through pin enable voltage regulator and standard interface such as SM (System Management) Bus and PM (Power Management) Bus. For this project, non-volatile Intel MAX 10 FPGA is used for power management controller. This FPGA include internal ADC (Analog to Digital Converter) and UFM (User Flash Memory) that is critical to design power management controller. Power management controller is running on NIOS II and Avalon-MM (Memory-Mapped) Bus is used to connect all the ADC, UFM, timer, UART (Universal Asynchronous Receiver/Transmitter), PWM (Pulse Width Modulation) and PM Bus. This project is to power up and power down the PM Bus compatible voltage regulator within the POR specification which is 200 us to 100 ms and achieve 100 ms power down for FPGA. There are a number of advantages using Intel MAX 10 FPGA such as built in ADC, UFM, flexibility of FPGA, and NIOS II soft processor.
format	Thesis
qualification_level	Master's degree
author	Ooi , Kheng Jin
author_facet	Ooi , Kheng Jin
author_sort	Ooi , Kheng Jin
title	Power Management Controller By Using Intel Max 10 Fpga
title_short	Power Management Controller By Using Intel Max 10 Fpga
title_full	Power Management Controller By Using Intel Max 10 Fpga
title_fullStr	Power Management Controller By Using Intel Max 10 Fpga
title_full_unstemmed	Power Management Controller By Using Intel Max 10 Fpga
title_sort	power management controller by using intel max 10 fpga
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/39565/1/OOI_KHENG_JIN_24_Pages.pdf
_version_	1747820759641751552

Power Management Controller By Using Intel Max 10 Fpga

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