Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work

Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Tran...

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Main Author:	Pragasam, Matthew
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf
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id	my-usm-ep.39594
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spelling	my-usm-ep.395942019-04-12T05:25:05Z Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work 2017 Pragasam, Matthew TK1-9971 Electrical engineering. Electronics. Nuclear engineering Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Transfer Level (RTL) level to form a suspected boundary consisting of multiple logics from one end to the other, layout to schematic mapping automation tool helps to identify fault in design within given boundary. Therefore the development of a path extractor program which is capable of extracting all possible paths from these start to end signals can save engineers time in tracing components involved between a fault line. This feature is extremely significant in Electronic Design Automation (EDA) as it can provide results of net name sequences stored in a database of mapper files. These mapper files can be used in layout design debug as the net sequence represents schematic signals. To be able to retrieve all possible signals involved within a suspected boundary is a popular search computational problem. Therefore the path extractor program proposed incorporates the characteristics of a depth-first search algorithm by considering the specifications of a cell-based design. The objectives achieved in this research are proven reliable with path extraction results consistent even with search depth manipulation. Performance differs an average of 12.6 % (iteration count) with keeping maximum allowable depth of search constant. Paths of net sequences were consistent throughout the verification of the path extractor program. This development and study of the path extract method carries significance in areas of EDA and debug diagnosis work. 2017 Thesis http://eprints.usm.my/39594/ http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Pragasam, Matthew Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
description	Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Transfer Level (RTL) level to form a suspected boundary consisting of multiple logics from one end to the other, layout to schematic mapping automation tool helps to identify fault in design within given boundary. Therefore the development of a path extractor program which is capable of extracting all possible paths from these start to end signals can save engineers time in tracing components involved between a fault line. This feature is extremely significant in Electronic Design Automation (EDA) as it can provide results of net name sequences stored in a database of mapper files. These mapper files can be used in layout design debug as the net sequence represents schematic signals. To be able to retrieve all possible signals involved within a suspected boundary is a popular search computational problem. Therefore the path extractor program proposed incorporates the characteristics of a depth-first search algorithm by considering the specifications of a cell-based design. The objectives achieved in this research are proven reliable with path extraction results consistent even with search depth manipulation. Performance differs an average of 12.6 % (iteration count) with keeping maximum allowable depth of search constant. Paths of net sequences were consistent throughout the verification of the path extractor program. This development and study of the path extract method carries significance in areas of EDA and debug diagnosis work.
format	Thesis
qualification_level	Master's degree
author	Pragasam, Matthew
author_facet	Pragasam, Matthew
author_sort	Pragasam, Matthew
title	Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
title_short	Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
title_full	Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
title_fullStr	Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
title_full_unstemmed	Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
title_sort	very large scale integration cell based path extractor for physical to layout mapping in fault isolation work
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf
_version_	1747820762805305344

Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work

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