Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach

Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach

Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana...

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Main Author: Chew , Ming Choo
Format: Thesis
Language:English
Published: 2013
Subjects:
T Technology
TK7800-8360 Electronics
Online Access:http://eprints.usm.my/40694/1/Design_Of_Fpga_Address_Register_In_28nm_Process_Technology_Based_On_Standard_Cell_Based_Approach.pdf
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spelling my-usm-ep.406942018-06-05T04:11:58Z Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach 2013-07 Chew , Ming Choo T Technology TK7800-8360 Electronics Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana kitaran reka bentuk meningkat dan merumitkan yang membawa kepada masa lelaran lanjut ke atas penutupan masa blok. Terdapat pelbagai jenis cabaran yang terpaksa dihadapi dalam proses 28nm dan seterusnya sekiranya pendekatan “full custom” masih digunakan untuk merekabentuk FPGA AR. Oleh itu, pendekatan berasaskan sel piawai digunakan untuk reka bentuk FPGA AR. Kitaran reka bentuk FPGA AR dapat dikurangkan dari bulan ke minggu dengan penggunaan kaedah sel piawai. Selain itu, penutupan masa dapat mengawal senario masa yang lebih. Keputusan menunjukkan bahawa FPGA AR menggunakan pendekatan berasaskan sel piawai adalah memenuhi spesifikasi reka bentuk yang diberikan. Di samping itu, jatuhan IR untuk kuasa dan bumi adalah di bawah 2mV, frekuensi adalah 330 MHz dan keluasan kawasan adalah 0.975mm2. Sebagai kesimpulan, pendekatan berasaskan sel piawai memberi pereka lebih banyak masa untuk menyelesaikan isu yang berkaitan dengan rekabentuk. Di samping itu, perubahan yang disebabkan oleh proses, voltan dan suhu dapat diperbaiki melalui kaedah pelbagai sudut dan senario ke atas FPGA AR. ________________________________________________________________________________________________________________________ Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is designed using full custom approach. With geometries shrink on advance process node, there is a need to reconsider the design approach used to design FPGA AR because of increased design cycle and complexity that lead to more iteration time on closing block timing. Significant design effort and challenges are required in 28nm and beyond when using full custom approach. Therefore, standard cell based approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from months to weeks with the automated standard cell based approach. Besides that, timing closure is able to cover more timing scenarios. Results show that FPGA AR using standard cell based approach is meeting the given design specification. IR drop on both power and ground is achieving less than 2mV per rail, frequency of 330MHz is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell based approach gives designer more time to focus on resolving design issues, and close the design in more timing scenarios which cover more design corners to improve variation due to process, voltage and temperature. 2013-07 Thesis http://eprints.usm.my/40694/ http://eprints.usm.my/40694/1/Design_Of_Fpga_Address_Register_In_28nm_Process_Technology_Based_On_Standard_Cell_Based_Approach.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik Dan Elektronik
institution Universiti Sains Malaysia
collection USM Institutional Repository
language English
topic T Technology
TK7800-8360 Electronics
spellingShingle T Technology
TK7800-8360 Electronics
Chew , Ming Choo
Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
description Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana kitaran reka bentuk meningkat dan merumitkan yang membawa kepada masa lelaran lanjut ke atas penutupan masa blok. Terdapat pelbagai jenis cabaran yang terpaksa dihadapi dalam proses 28nm dan seterusnya sekiranya pendekatan “full custom” masih digunakan untuk merekabentuk FPGA AR. Oleh itu, pendekatan berasaskan sel piawai digunakan untuk reka bentuk FPGA AR. Kitaran reka bentuk FPGA AR dapat dikurangkan dari bulan ke minggu dengan penggunaan kaedah sel piawai. Selain itu, penutupan masa dapat mengawal senario masa yang lebih. Keputusan menunjukkan bahawa FPGA AR menggunakan pendekatan berasaskan sel piawai adalah memenuhi spesifikasi reka bentuk yang diberikan. Di samping itu, jatuhan IR untuk kuasa dan bumi adalah di bawah 2mV, frekuensi adalah 330 MHz dan keluasan kawasan adalah 0.975mm2. Sebagai kesimpulan, pendekatan berasaskan sel piawai memberi pereka lebih banyak masa untuk menyelesaikan isu yang berkaitan dengan rekabentuk. Di samping itu, perubahan yang disebabkan oleh proses, voltan dan suhu dapat diperbaiki melalui kaedah pelbagai sudut dan senario ke atas FPGA AR. ________________________________________________________________________________________________________________________ Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is designed using full custom approach. With geometries shrink on advance process node, there is a need to reconsider the design approach used to design FPGA AR because of increased design cycle and complexity that lead to more iteration time on closing block timing. Significant design effort and challenges are required in 28nm and beyond when using full custom approach. Therefore, standard cell based approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from months to weeks with the automated standard cell based approach. Besides that, timing closure is able to cover more timing scenarios. Results show that FPGA AR using standard cell based approach is meeting the given design specification. IR drop on both power and ground is achieving less than 2mV per rail, frequency of 330MHz is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell based approach gives designer more time to focus on resolving design issues, and close the design in more timing scenarios which cover more design corners to improve variation due to process, voltage and temperature.
format Thesis
qualification_level Master's degree
author Chew , Ming Choo
author_facet Chew , Ming Choo
author_sort Chew , Ming Choo
title Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
title_short Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
title_full Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
title_fullStr Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
title_full_unstemmed Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
title_sort design of fpga address register in 28nm process technology based on standard cell based approach
granting_institution Universiti Sains Malaysia
granting_department Pusat Pengajian Kejuruteraan Elektrik Dan Elektronik
publishDate 2013
url http://eprints.usm.my/40694/1/Design_Of_Fpga_Address_Register_In_28nm_Process_Technology_Based_On_Standard_Cell_Based_Approach.pdf
_version_ 1747820804245028864

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