A Study On Power Reduction Techniques For Comparator Based On Body Biasing
The growth of portable electronic devices in consumer market has led to the innovation of low power design. Furthermore, the scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per area unit. Hence...
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my-usm-ep.407452018-06-11T08:11:12Z A Study On Power Reduction Techniques For Comparator Based On Body Biasing 2014 Osman, Nor Fatihah TK1-9971 Electrical engineering. Electronics. Nuclear engineering The growth of portable electronic devices in consumer market has led to the innovation of low power design. Furthermore, the scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per area unit. Hence power reduction technique is being explored in electronic integrated circuit design. In flash analog to digital converter (ADC), comparator consumes the most power. In this dissertation, power reductions techniques such as sleepy transistor technique, stack transistor technique and body biasing technique are studied. A conventional comparator, comparator reduced VDD and comparator with super cut-off CMOS (SCCMOS) and sleepy stack are implanted using 0.13 μm CMOS process technology. Then, a low power comparator is proposed using body biasing technique, sleepy stack transistor and super cut-off CMOS. Forward body biasing technique is used to decrease the threshold voltage. As a result, VDD is able to reduce. Hence, dynamic power consumption also reduced. Meanwhile, SCCMOS and sleepy stack transistor are used to reduce leakage current. As a consequence, the static power is reduced. From pre-layout simulation of proposed comparator, the static power is 94.66 pW compared to 404.2 μW for conventional comparator. Meanwhile, the dynamic power for proposed comparator is 14.76 μW compared 1.127 mV for conventional comparator. The pre-layout xiv simulation and post-layout simulation show there is no significant parasitic effect on the performance of proposed comparator. 2014 Thesis http://eprints.usm.my/40745/ http://eprints.usm.my/40745/1/NOR_FATIHAH_BINTI_OSMAN_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Awam |
| institution |
Universiti Sains Malaysia |
| collection |
USM Institutional Repository |
| language |
English |
| topic |
TK1-9971 Electrical engineering Electronics Nuclear engineering |
| spellingShingle |
TK1-9971 Electrical engineering Electronics Nuclear engineering Osman, Nor Fatihah A Study On Power Reduction Techniques For Comparator Based On Body Biasing |
| description |
The growth of portable electronic devices in consumer market has led to the innovation of low power design. Furthermore, the scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per area unit. Hence power reduction technique is being explored in electronic integrated circuit
design. In flash analog to digital converter (ADC), comparator consumes the most power. In this dissertation, power reductions techniques such as sleepy transistor technique, stack transistor technique and body biasing technique are studied. A conventional comparator, comparator reduced VDD and comparator with super cut-off CMOS (SCCMOS) and sleepy stack are implanted using 0.13 μm CMOS process technology. Then, a low power comparator is proposed using body biasing technique, sleepy stack transistor and super cut-off CMOS. Forward body biasing technique is used to decrease the threshold voltage. As a result, VDD is able to reduce. Hence, dynamic power consumption also reduced. Meanwhile, SCCMOS and sleepy stack transistor are used to reduce leakage current. As a consequence, the static power is reduced. From pre-layout simulation of proposed comparator, the static power is 94.66 pW compared to 404.2 μW for conventional comparator. Meanwhile, the dynamic power for proposed
comparator is 14.76 μW compared 1.127 mV for conventional comparator. The pre-layout xiv simulation and post-layout simulation show there is no significant parasitic effect on the performance of proposed comparator. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Osman, Nor Fatihah |
| author_facet |
Osman, Nor Fatihah |
| author_sort |
Osman, Nor Fatihah |
| title |
A Study On Power Reduction Techniques For Comparator Based On Body Biasing |
| title_short |
A Study On Power Reduction Techniques For Comparator Based On Body Biasing |
| title_full |
A Study On Power Reduction Techniques For Comparator Based On Body Biasing |
| title_fullStr |
A Study On Power Reduction Techniques For Comparator Based On Body Biasing |
| title_full_unstemmed |
A Study On Power Reduction Techniques For Comparator Based On Body Biasing |
| title_sort |
study on power reduction techniques for comparator based on body biasing |
| granting_institution |
Universiti Sains Malaysia |
| granting_department |
Pusat Pengajian Kejuruteraan Awam |
| publishDate |
2014 |
| url |
http://eprints.usm.my/40745/1/NOR_FATIHAH_BINTI_OSMAN_24_Pages.pdf |
| _version_ |
1747820813329891328 |