A Study On Power Reduction Techniques For Comparator Based On Body Biasing
The growth of portable electronic devices in consumer market has led to the innovation of low power design. Furthermore, the scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per area unit. Hence...
Saved in:
Main Author: | Osman, Nor Fatihah |
---|---|
Format: | Thesis |
Language: | English |
Published: |
2014
|
Subjects: | |
Online Access: | http://eprints.usm.my/40745/1/NOR_FATIHAH_BINTI_OSMAN_24_Pages.pdf |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Clock Gating Technique For Power Reduction In Digital Design
by: Khor, Peng Lim
Published: (2012) -
Improved Techniques For Power
Consumption Reduction In
Portable Two-Way Radio
by: Adrian, Lim Hooi Jin
Published: (2013) -
Peak To Average Power Ratio Reduction In
Wireless Orthogonal Frequency Division
Multiplexing
by: Wahab, Aeizaal Azman Abdul
Published: (2014) -
On The Analysis Of Mcm Systems Papr
Profiles And The Wp-Ofdm System Papr
Reduction Techniques
by: Zakaria, Jamaluddin
Published: (2013) -
Modified PWM Technique For Torque Ripples Reduction In
Three Phase PM BLDC Motors
by: Salah, Wael Abdel Muhdi Yacoup
Published: (2012)