Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect

This research highlights the development of test platform of FPGA interconnect to capture marginal open defect on Altera® Stratix V devices. The need for at-speed test was due to the increasing number of marginal open defects, resulting from manufacturing process complexity anticipated from continu...

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Main Author:	Mohamed Sultan, Fahmy Hafriz
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/40813/1/FAHMY_HAFRIZ_BIN_MOHAMED_SULTAN_24_pages.pdf
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id	my-usm-ep.40813
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spelling	my-usm-ep.408132018-06-26T04:56:22Z Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect 2015 Mohamed Sultan, Fahmy Hafriz TK7800-8360 Electronics This research highlights the development of test platform of FPGA interconnect to capture marginal open defect on Altera® Stratix V devices. The need for at-speed test was due to the increasing number of marginal open defects, resulting from manufacturing process complexity anticipated from continuously shrinking transistors towards nanometer (nm) scale. The defect was unable to be captured by current stuck-at test and this research utilized the Launch on Shift (LOS) transition delay method to detect the marginal open defects. Towards the final implementation, there are few unique design implemented in order to generate the at-speed clocks and the pipelined scan enable signals to support LOS method. Meanwhile, the ability to test the interconnect on at-speed frequency required new routing tool control variables to limit the interconnect path lengths and device power consumption. The control variables are discussed further in this research. The LOS test patterns used in this research managed to cover up to 81% of the overall routing resources for marginal open defect effectively. Furthermore, the test was successfully implemented at frequencies up to 400 MHz and proven to be sensitive to routing delay to capture marginal open defects. The ability to capture the defect with only 0.56 kΩ resistance is better than the initial 3 kΩ target in this research. It is also better than other literatures which targeted between 6 kΩ to 10 kΩ only. 2015 Thesis http://eprints.usm.my/40813/ http://eprints.usm.my/40813/1/FAHMY_HAFRIZ_BIN_MOHAMED_SULTAN_24_pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Mohamed Sultan, Fahmy Hafriz Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect
description	This research highlights the development of test platform of FPGA interconnect to capture marginal open defect on Altera® Stratix V devices. The need for at-speed test was due to the increasing number of marginal open defects, resulting from manufacturing process complexity anticipated from continuously shrinking transistors towards nanometer (nm) scale. The defect was unable to be captured by current stuck-at test and this research utilized the Launch on Shift (LOS) transition delay method to detect the marginal open defects. Towards the final implementation, there are few unique design implemented in order to generate the at-speed clocks and the pipelined scan enable signals to support LOS method. Meanwhile, the ability to test the interconnect on at-speed frequency required new routing tool control variables to limit the interconnect path lengths and device power consumption. The control variables are discussed further in this research. The LOS test patterns used in this research managed to cover up to 81% of the overall routing resources for marginal open defect effectively. Furthermore, the test was successfully implemented at frequencies up to 400 MHz and proven to be sensitive to routing delay to capture marginal open defects. The ability to capture the defect with only 0.56 kΩ resistance is better than the initial 3 kΩ target in this research. It is also better than other literatures which targeted between 6 kΩ to 10 kΩ only.
format	Thesis
qualification_level	Master's degree
author	Mohamed Sultan, Fahmy Hafriz
author_facet	Mohamed Sultan, Fahmy Hafriz
author_sort	Mohamed Sultan, Fahmy Hafriz
title	Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect
title_short	Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect
title_full	Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect
title_fullStr	Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect
title_full_unstemmed	Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect
title_sort	development of test platform of fpga interconnect to capture marginal open defect
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2015
url	http://eprints.usm.my/40813/1/FAHMY_HAFRIZ_BIN_MOHAMED_SULTAN_24_pages.pdf
_version_	1747820828275245056

Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect

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