Tan , A. H. (2015). Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging.
Chicago Style (17th ed.) CitationTan , Ai Heong. Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging. 2015.
MLA (8th ed.) CitationTan , Ai Heong. Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging. 2015.
Warning: These citations may not always be 100% accurate.