Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC...

Full description

Saved in:

Bibliographic Details
Main Author:	Tan , Ai Heong
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-usm-ep.40931
record_format	uketd_dc
spelling	my-usm-ep.409312018-07-05T08:55:04Z Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging 2015 Tan , Ai Heong TK1-9971 Electrical engineering. Electronics. Nuclear engineering In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC). Moreover, the signaling techniques play a crucial role in determining the overall performance of a device. Thus, this thesis explores an innovative concept of vertical side-chip interconnection (VSCI) for 3 dimension (3D) packaging to improve the performance of IC. The electrical performance of the proposed vertical side-chip stacked package is discussed in order to optimize the structure of VSCI. Optimization of VSCI structure is based on stacked die package application with the trending of through silicon via (TSV) signal orientation, TSV signal to ground ratio and TSV signal pitch impact to the overall signal integrity performance. Then, this thesis had underscored the electrical performance of the aforementioned stacked die packages from signal integrity perspective in terms of impedance matching, noise shielding and electrical losses. Then, the sensitivity study of channel termination on vertical side-chip interconnection (VSCI) was carried out. The conventional 3D integrated system with solder bump and surface activated bonding (SAB) technology also was investigated as comparison with VSCI. The trends of eye height opening and one of the critical signaling parameters were analyzed based on transmission channel length, input rise time, receiver device capacitance and termination resistance factors. Finally, full wave simulation using 3D electromagnetic field solvers and transient analysis results showed the feasibility of VSCI as alternative method to achieve comparable electrical performance with the conventional solder bump and SAB interconnection models at 100Gbps transfer rate. The simulation results showed potential solution space of VSCI for weak receiver termination to achieve more 350mV eye height opening (based on 1V supply voltage) at 30Gbps. 2015 Thesis http://eprints.usm.my/40931/ http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Tan , Ai Heong Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
description	In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC). Moreover, the signaling techniques play a crucial role in determining the overall performance of a device. Thus, this thesis explores an innovative concept of vertical side-chip interconnection (VSCI) for 3 dimension (3D) packaging to improve the performance of IC. The electrical performance of the proposed vertical side-chip stacked package is discussed in order to optimize the structure of VSCI. Optimization of VSCI structure is based on stacked die package application with the trending of through silicon via (TSV) signal orientation, TSV signal to ground ratio and TSV signal pitch impact to the overall signal integrity performance. Then, this thesis had underscored the electrical performance of the aforementioned stacked die packages from signal integrity perspective in terms of impedance matching, noise shielding and electrical losses. Then, the sensitivity study of channel termination on vertical side-chip interconnection (VSCI) was carried out. The conventional 3D integrated system with solder bump and surface activated bonding (SAB) technology also was investigated as comparison with VSCI. The trends of eye height opening and one of the critical signaling parameters were analyzed based on transmission channel length, input rise time, receiver device capacitance and termination resistance factors. Finally, full wave simulation using 3D electromagnetic field solvers and transient analysis results showed the feasibility of VSCI as alternative method to achieve comparable electrical performance with the conventional solder bump and SAB interconnection models at 100Gbps transfer rate. The simulation results showed potential solution space of VSCI for weak receiver termination to achieve more 350mV eye height opening (based on 1V supply voltage) at 30Gbps.
format	Thesis
qualification_level	Master's degree
author	Tan , Ai Heong
author_facet	Tan , Ai Heong
author_sort	Tan , Ai Heong
title	Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
title_short	Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
title_full	Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
title_fullStr	Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
title_full_unstemmed	Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
title_sort	modeling of vertical side chip interconnect technology for 3-dimensional packaging
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2015
url	http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf
_version_	1747820841989570560

Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

Similar Items