Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC...

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书目详细资料
主要作者:	Tan , Ai Heong
格式:	Thesis
语言:	English
出版:	2015
主题:	TK1-9971 Electrical engineering Electronics Nuclear engineering
在线阅读:	http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf
标签:	添加标签没有标签, 成为第一个标记此记录!

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