New Cdc Design Tool For Analog Layout Workflow
The placement and routing on CMOS analog layout design had always been a time consuming and irritating process due to large amount of transistor devices placements, arrangements and a lot of critical nets routing constraint. Manual efforts to complete analog layout design took few weeks to months’ t...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2015
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| 主題: | |
| 在線閱讀: | http://eprints.usm.my/40966/1/NG_HIN_MUNG_24_pages.pdf |
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