Development Of Laser Assisted Device Alteration (Lada) Technique For Failure Region Identification In Integrated Circuit
The purpose of this research is to create a solution for some of the obstacles faced during Integrated Circuit (IC) Failure Analysis (FA). Faults in ICs increase proportionally with the growing number of transistors, narrower process margins and increasing complexity of IC design. The IC industry de...
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| 格式: | Thesis |
| 语言: | English |
| 出版: |
2015
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| 主题: | |
| 在线阅读: | http://eprints.usm.my/40968/1/THOR_MAN_HON_24_pages.pdf |
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| 总结: | The purpose of this research is to create a solution for some of the obstacles faced during Integrated Circuit (IC) Failure Analysis (FA). Faults in ICs increase proportionally with the growing number of transistors, narrower process margins and increasing complexity of IC design. The IC industry depends heavily on FA to drive the time to market, yield and reliability learning, experiment evaluation and technology qualification. However, current FA flow is not straight forward and robust enough to solve every IC failure type, especially in solid failing cases. Therefore, a Laser Assisted Device Alteration (LADA) technique combined with Perl scripting that works on Automated Testing Equipment (ATE) is proposed in this study to solve the obstacles faced during FA. The said Perl script will act as a looping agent, test result comparator, triggering controller to enable LADA scanning and to find the sensitive transistor or circuit device towards the failure. Results from some actual case studies proved that the proposed technique can work with design as well as defect based failures, either through structural or functional tests which also needs consideration of specific sensitive circuitry within the IC design. As a conclusion, the contribution of the proposed technique is its ability to resolve solid failure problems in ICs, the capability to pin point the defective area to within a small region of up to a single transistor size and finally to simplify the entire FA process for a 3D FinFET System on Chip (SoC) IC. |
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