Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application
This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter. The specification of the operational amplifier is 40dB of gain, and 1MHz cut-off frequency. Silterra 0.13um process technology is used in this work. The amplifier topology used in this research is Fo...
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2014
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| 主題: | |
| 在線閱讀: | http://eprints.usm.my/41078/1/TENG_JIN_CHUNG_24_Pages.pdf |
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| 總結: | This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter. The specification of the operational amplifier is 40dB of gain, and 1MHz cut-off frequency. Silterra 0.13um process technology is used in this work. The amplifier topology used in this research is Folded cascode which gives larger output swing. Differential pairs Common-mode feedback is used to overcome the mismatch of source current and to fix the folded cascode output voltage level at 350mV. The proposed design was able to achieve DC gain of 44.77dB and 1.06MHz cut-off frequency. The designed amplifier power consumption is very low, which is 9.598mW. Figure of merit of this design are |
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