Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design

Transistor sizing had been scaled down to increase the number of transistors in a single chip which also leads to the variation of IP blocks. Consequently, the layout design becomes very complex and it is challenging to verify the layout design. Therefore, the option layer had been identified where...

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Main Author:	Oothayer Kumar, Sureindra Kumar
Format:	Thesis
Language:	English
Published:	2014
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41152/1/SUREINDRA_KUMAR_AL_OOTHAYER_KUMAR_24_Pages.pdf
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id	my-usm-ep.41152
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spelling	my-usm-ep.411522018-07-25T08:04:38Z Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design 2014 Oothayer Kumar, Sureindra Kumar TK7800-8360 Electronics Transistor sizing had been scaled down to increase the number of transistors in a single chip which also leads to the variation of IP blocks. Consequently, the layout design becomes very complex and it is challenging to verify the layout design. Therefore, the option layer had been identified where it will have a common base circuitry and layout. After the layout is completed, it is very convenient to convert the option metal and via to real metal and via layer. However, the conventional verification using the design rule check (DRC) in Cadence does not include the check for option layer. Option layer on preprogrammed layout are not verified correct and may cause a violation. Thus, this project will enable the verification of the option layer by developing an algorithm which able to cover the check for both option and real metal/via layer. This project will be based on TSMC 20nm process library and the modifications are made to enable the option layer check. In order to enable the modification to be made quickly and enable worst case check, Practical Extraction and Report Language (PERL) programming used to automate the code. The result is shown by drawing the test pattern with design rule. As example, a rule with specification of more than or equal with 0.05nm will flag an error if the test pattern is drawn less than 0.05nm. This approach had been applied to all the design rules involved in 20nm process technology. The method proposed validates the option layer successfully and most errors found in the early stage of designing the layout are minimized. 2014 Thesis http://eprints.usm.my/41152/ http://eprints.usm.my/41152/1/SUREINDRA_KUMAR_AL_OOTHAYER_KUMAR_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Oothayer Kumar, Sureindra Kumar Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
description	Transistor sizing had been scaled down to increase the number of transistors in a single chip which also leads to the variation of IP blocks. Consequently, the layout design becomes very complex and it is challenging to verify the layout design. Therefore, the option layer had been identified where it will have a common base circuitry and layout. After the layout is completed, it is very convenient to convert the option metal and via to real metal and via layer. However, the conventional verification using the design rule check (DRC) in Cadence does not include the check for option layer. Option layer on preprogrammed layout are not verified correct and may cause a violation. Thus, this project will enable the verification of the option layer by developing an algorithm which able to cover the check for both option and real metal/via layer. This project will be based on TSMC 20nm process library and the modifications are made to enable the option layer check. In order to enable the modification to be made quickly and enable worst case check, Practical Extraction and Report Language (PERL) programming used to automate the code. The result is shown by drawing the test pattern with design rule. As example, a rule with specification of more than or equal with 0.05nm will flag an error if the test pattern is drawn less than 0.05nm. This approach had been applied to all the design rules involved in 20nm process technology. The method proposed validates the option layer successfully and most errors found in the early stage of designing the layout are minimized.
format	Thesis
qualification_level	Master's degree
author	Oothayer Kumar, Sureindra Kumar
author_facet	Oothayer Kumar, Sureindra Kumar
author_sort	Oothayer Kumar, Sureindra Kumar
title	Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
title_short	Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
title_full	Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
title_fullStr	Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
title_full_unstemmed	Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
title_sort	design rule check to validate option metal and via for a preprogrammed layout design
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2014
url	http://eprints.usm.my/41152/1/SUREINDRA_KUMAR_AL_OOTHAYER_KUMAR_24_Pages.pdf
_version_	1747820883644252160

Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design

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