Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design
Transistor sizing had been scaled down to increase the number of transistors in a single chip which also leads to the variation of IP blocks. Consequently, the layout design becomes very complex and it is challenging to verify the layout design. Therefore, the option layer had been identified where...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2014
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| Subjects: | |
| Online Access: | http://eprints.usm.my/41152/1/SUREINDRA_KUMAR_AL_OOTHAYER_KUMAR_24_Pages.pdf |
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