Reduced Galloping Column Algorithm For Memory Testing

Memory testing is significantly important nowadays especially in SOC’s design, due to their rapid growth in the memory density and design complexity in smaller chip area and low power design. Thus, test time in memory testing is a key challenge to accelerate time to market, high yield and low test...

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Main Author:	Ngieng , Siew Ching
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41214/1/Ngieng_Siew_Ching__24_Pages.pdf
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id	my-usm-ep.41214
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spelling	my-usm-ep.412142018-07-31T08:05:38Z Reduced Galloping Column Algorithm For Memory Testing 2015 Ngieng , Siew Ching TK7800-8360 Electronics Memory testing is significantly important nowadays especially in SOC’s design, due to their rapid growth in the memory density and design complexity in smaller chip area and low power design. Thus, test time in memory testing is a key challenge to accelerate time to market, high yield and low test cost in high volume manufacturing. Test time reduction in memory testing is important in industry, as test cost is directly related to validation time of each product on the tester. There are lots of memory algorithms used for memory testing, including the galloping column algorithm (GalCol). The GalCol algorithm test is important to detect unique coupling and transition faults. However, the existing GalCol algorithm takes huge test time due to its test complexity. To overcome the test time issue in industry, reduced GalCol algorithms with solid data background are proposed. The reduced GalCol algoritms have similar test behavior as original GalCol algorithm with major difference in the number of galloping of the target cells. The galloping of target cells are reduced to first and last 8, 16 and 32 of cells of every base cell. This project is progressed in two stages, which are the software development using INTEL software and Synopsys tool and test implementation on INTEL production flow. These algorithm are verified on 15 units of 64KB L2 SRAM memory. In this project, test time reduction and consistent pass fail test results are achieved in the reduced GalCol algorithm tests. The GalCol X8 algorithm obtains the highest test time reduction of about 79.5% at 600MHz and 75.7% at 1.6GHz with consistent pass or fail test results comparable to original GalCol algorithm in the HVM test flow. 2015 Thesis http://eprints.usm.my/41214/ http://eprints.usm.my/41214/1/Ngieng_Siew_Ching__24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Ngieng , Siew Ching Reduced Galloping Column Algorithm For Memory Testing
description	Memory testing is significantly important nowadays especially in SOC’s design, due to their rapid growth in the memory density and design complexity in smaller chip area and low power design. Thus, test time in memory testing is a key challenge to accelerate time to market, high yield and low test cost in high volume manufacturing. Test time reduction in memory testing is important in industry, as test cost is directly related to validation time of each product on the tester. There are lots of memory algorithms used for memory testing, including the galloping column algorithm (GalCol). The GalCol algorithm test is important to detect unique coupling and transition faults. However, the existing GalCol algorithm takes huge test time due to its test complexity. To overcome the test time issue in industry, reduced GalCol algorithms with solid data background are proposed. The reduced GalCol algoritms have similar test behavior as original GalCol algorithm with major difference in the number of galloping of the target cells. The galloping of target cells are reduced to first and last 8, 16 and 32 of cells of every base cell. This project is progressed in two stages, which are the software development using INTEL software and Synopsys tool and test implementation on INTEL production flow. These algorithm are verified on 15 units of 64KB L2 SRAM memory. In this project, test time reduction and consistent pass fail test results are achieved in the reduced GalCol algorithm tests. The GalCol X8 algorithm obtains the highest test time reduction of about 79.5% at 600MHz and 75.7% at 1.6GHz with consistent pass or fail test results comparable to original GalCol algorithm in the HVM test flow.
format	Thesis
qualification_level	Master's degree
author	Ngieng , Siew Ching
author_facet	Ngieng , Siew Ching
author_sort	Ngieng , Siew Ching
title	Reduced Galloping Column Algorithm For Memory Testing
title_short	Reduced Galloping Column Algorithm For Memory Testing
title_full	Reduced Galloping Column Algorithm For Memory Testing
title_fullStr	Reduced Galloping Column Algorithm For Memory Testing
title_full_unstemmed	Reduced Galloping Column Algorithm For Memory Testing
title_sort	reduced galloping column algorithm for memory testing
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2015
url	http://eprints.usm.my/41214/1/Ngieng_Siew_Ching__24_Pages.pdf
_version_	1747820889033932800

Reduced Galloping Column Algorithm For Memory Testing

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