Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
High speed serial protocols build upon multi-gigabit transceivers in the FPGA are the backbone of data communication industries. These protocols are now a fundamental requirement for today’s applications as well as addressing the needs of next generation systems. However, transferring command and s...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2016
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/41306/1/LOH_MUI_SOON_24_Pages.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | High speed serial protocols build upon multi-gigabit transceivers in the FPGA are the backbone of data communication industries. These protocols are now a
fundamental requirement for today’s applications as well as addressing the needs of next generation systems. However, transferring command and status packets
explicitly in inter-FPGA control links efficiently via multi-gigabit transceivers without wasting data bandwidth become a challenge when architecting a modern design. Though time-division-multiplexing techniques could be deployed to address this issue, dedicated but unused time-slots for control link packets adversely affect the
bandwidth efficiency and thus the system performance. Another common solution focuses on transferring the command and status packets in a separate control link;
typically implemented in low to medium bandwidth serial protocols such as I2C and SPI. Though this solution is simple to implement in hardware with readily available
device drivers, an unnecessary high latency overhead is introduced such as when transferring a 512-byte filter data coefficients to configure a 128-tap FIR filter. In this dissertation, a highly efficient, low latency command-status packet tunneling architecture built on top of the 25 Gbps Interlaken serial protocol for multi-gigabit inter-FPGA data streaming is proposed. Simulation results show that the proposed architecture works successfully with a high efficiency, utilizes only 13.21% and 10.34% of the clock cycles required in the conventional SPI and I2C implementations respectively. The proposed architecture also maintains a backward compatibility with control links implemented separately using SPI or I2C serial protocols to simplify the
overall system design, reduce product development risks and system costs. |
|---|