Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture

High speed serial protocols build upon multi-gigabit transceivers in the FPGA are the backbone of data communication industries. These protocols are now a fundamental requirement for today’s applications as well as addressing the needs of next generation systems. However, transferring command and s...

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Main Author:	Loh, Mui Soon
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK7870 Electronic packaging
Online Access:	http://eprints.usm.my/41306/1/LOH_MUI_SOON_24_Pages.pdf
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id	my-usm-ep.41306
record_format	uketd_dc
spelling	my-usm-ep.413062018-08-13T08:54:02Z Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture 2016 Loh, Mui Soon TK7870 Electronic packaging High speed serial protocols build upon multi-gigabit transceivers in the FPGA are the backbone of data communication industries. These protocols are now a fundamental requirement for today’s applications as well as addressing the needs of next generation systems. However, transferring command and status packets explicitly in inter-FPGA control links efficiently via multi-gigabit transceivers without wasting data bandwidth become a challenge when architecting a modern design. Though time-division-multiplexing techniques could be deployed to address this issue, dedicated but unused time-slots for control link packets adversely affect the bandwidth efficiency and thus the system performance. Another common solution focuses on transferring the command and status packets in a separate control link; typically implemented in low to medium bandwidth serial protocols such as I2C and SPI. Though this solution is simple to implement in hardware with readily available device drivers, an unnecessary high latency overhead is introduced such as when transferring a 512-byte filter data coefficients to configure a 128-tap FIR filter. In this dissertation, a highly efficient, low latency command-status packet tunneling architecture built on top of the 25 Gbps Interlaken serial protocol for multi-gigabit inter-FPGA data streaming is proposed. Simulation results show that the proposed architecture works successfully with a high efficiency, utilizes only 13.21% and 10.34% of the clock cycles required in the conventional SPI and I2C implementations respectively. The proposed architecture also maintains a backward compatibility with control links implemented separately using SPI or I2C serial protocols to simplify the overall system design, reduce product development risks and system costs. 2016 Thesis http://eprints.usm.my/41306/ http://eprints.usm.my/41306/1/LOH_MUI_SOON_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7870 Electronic packaging
spellingShingle	TK7870 Electronic packaging Loh, Mui Soon Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
description	High speed serial protocols build upon multi-gigabit transceivers in the FPGA are the backbone of data communication industries. These protocols are now a fundamental requirement for today’s applications as well as addressing the needs of next generation systems. However, transferring command and status packets explicitly in inter-FPGA control links efficiently via multi-gigabit transceivers without wasting data bandwidth become a challenge when architecting a modern design. Though time-division-multiplexing techniques could be deployed to address this issue, dedicated but unused time-slots for control link packets adversely affect the bandwidth efficiency and thus the system performance. Another common solution focuses on transferring the command and status packets in a separate control link; typically implemented in low to medium bandwidth serial protocols such as I2C and SPI. Though this solution is simple to implement in hardware with readily available device drivers, an unnecessary high latency overhead is introduced such as when transferring a 512-byte filter data coefficients to configure a 128-tap FIR filter. In this dissertation, a highly efficient, low latency command-status packet tunneling architecture built on top of the 25 Gbps Interlaken serial protocol for multi-gigabit inter-FPGA data streaming is proposed. Simulation results show that the proposed architecture works successfully with a high efficiency, utilizes only 13.21% and 10.34% of the clock cycles required in the conventional SPI and I2C implementations respectively. The proposed architecture also maintains a backward compatibility with control links implemented separately using SPI or I2C serial protocols to simplify the overall system design, reduce product development risks and system costs.
format	Thesis
qualification_level	Master's degree
author	Loh, Mui Soon
author_facet	Loh, Mui Soon
author_sort	Loh, Mui Soon
title	Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
title_short	Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
title_full	Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
title_fullStr	Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
title_full_unstemmed	Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture
title_sort	highly efficient multi-gigabit commandstatus packet tunneling technique in inter-fpga packet streaming architecture
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2016
url	http://eprints.usm.my/41306/1/LOH_MUI_SOON_24_Pages.pdf
_version_	1747820906953048064

Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture

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