Implementation Of Write Assist Technique On Low Voltage Distributed Memory

In scaled technology nodes and scaled supply voltages, the SRAM write ability is being degraded and becomes a critical design concern. Various write assist techniques are developed to improve SRAM write ability. In this study, an improved write assist technique that implements the conventional boost...

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Main Author:	Chan, Gaik Ming
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41310/1/CHAN_GAIK_MING_24_Pages.pdf
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spelling	my-usm-ep.413102018-08-14T02:21:24Z Implementation Of Write Assist Technique On Low Voltage Distributed Memory 2016 Chan, Gaik Ming TK7800-8360 Electronics In scaled technology nodes and scaled supply voltages, the SRAM write ability is being degraded and becomes a critical design concern. Various write assist techniques are developed to improve SRAM write ability. In this study, an improved write assist technique that implements the conventional boosted word-line voltage idea on the Dual-VT SRAM cell is proposed. By adopting the low threshold voltage write access transistors in the proposed technique, the comparable write access time as the conventional technique could be achieved with the lower boosted voltage. The lower boosted voltage on word-line drivers could help in static and dynamic power reductions. However, the proposed technique has drawback of higher static power on SRAM cell due to the adoption of low threshold voltage transistor. The SPICE simulation has been performed to evaluate the write performance and power consumption of the conventional and proposed techniques for comparative study. The simulation results have shown that a lower boosted voltage could be applied on lower threshold voltage write access transistor with 1% to 2% improvement as compared to the conventional technique. The boosted voltages for Std-VT, Low-VT and Ultra-Low-VT write access transistors are 1.00V, 0.94V and 0.90V respectively. When SRAM write operation is activated, there is an average of 6% total power reduction observed with the implementation of Low-VT write access transistor. The implementation of Ultra-Low-VT write access transistor produces 10% of total power reduction. When SRAM write operation is inactivated, the Low-VT write access transistor implementation could save 7% total power consumption. However, the implementation of Ultra-Low-VT write access transistor causes up to 4% total power increment. As a result, the proposed write assist technique is suitable for the low voltage distributed memory in the applications of high speed and high activity of memory write operation. 2016 Thesis http://eprints.usm.my/41310/ http://eprints.usm.my/41310/1/CHAN_GAIK_MING_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Chan, Gaik Ming Implementation Of Write Assist Technique On Low Voltage Distributed Memory
description	In scaled technology nodes and scaled supply voltages, the SRAM write ability is being degraded and becomes a critical design concern. Various write assist techniques are developed to improve SRAM write ability. In this study, an improved write assist technique that implements the conventional boosted word-line voltage idea on the Dual-VT SRAM cell is proposed. By adopting the low threshold voltage write access transistors in the proposed technique, the comparable write access time as the conventional technique could be achieved with the lower boosted voltage. The lower boosted voltage on word-line drivers could help in static and dynamic power reductions. However, the proposed technique has drawback of higher static power on SRAM cell due to the adoption of low threshold voltage transistor. The SPICE simulation has been performed to evaluate the write performance and power consumption of the conventional and proposed techniques for comparative study. The simulation results have shown that a lower boosted voltage could be applied on lower threshold voltage write access transistor with 1% to 2% improvement as compared to the conventional technique. The boosted voltages for Std-VT, Low-VT and Ultra-Low-VT write access transistors are 1.00V, 0.94V and 0.90V respectively. When SRAM write operation is activated, there is an average of 6% total power reduction observed with the implementation of Low-VT write access transistor. The implementation of Ultra-Low-VT write access transistor produces 10% of total power reduction. When SRAM write operation is inactivated, the Low-VT write access transistor implementation could save 7% total power consumption. However, the implementation of Ultra-Low-VT write access transistor causes up to 4% total power increment. As a result, the proposed write assist technique is suitable for the low voltage distributed memory in the applications of high speed and high activity of memory write operation.
format	Thesis
qualification_level	Master's degree
author	Chan, Gaik Ming
author_facet	Chan, Gaik Ming
author_sort	Chan, Gaik Ming
title	Implementation Of Write Assist Technique On Low Voltage Distributed Memory
title_short	Implementation Of Write Assist Technique On Low Voltage Distributed Memory
title_full	Implementation Of Write Assist Technique On Low Voltage Distributed Memory
title_fullStr	Implementation Of Write Assist Technique On Low Voltage Distributed Memory
title_full_unstemmed	Implementation Of Write Assist Technique On Low Voltage Distributed Memory
title_sort	implementation of write assist technique on low voltage distributed memory
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2016
url	http://eprints.usm.my/41310/1/CHAN_GAIK_MING_24_Pages.pdf
_version_	1747820907935563776

Implementation Of Write Assist Technique On Low Voltage Distributed Memory

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