Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect

As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration...

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Main Author:	Chiew , Chong Giap
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf
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spelling	my-usm-ep.413122018-08-14T04:08:47Z Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect 2016 Chiew , Chong Giap TK7800-8360 Electronics As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration of multiple die on a single chip. Communication between die requires full network-on-chip (NoC) which is area intensive. In deep sub-micron process nodes, high speed signaling between multiple die becomes one of the main challenges in multidie chip design. Methods to increase the routability have been proposed as the use of parallel interconnect appears to be the bottleneck of high speed multidie communication. Conversion of parallel data bits into serial data streams before transmission effectively reduced the number of wires required for the interconnect. Synchronous serial transmission requires large design dimension and power hungry auxiliary blocks for synchronization between the transmitted data and clock signals. This is avoided with the implementation of self-timed transmission scheme which eliminates the need to transmit the clock signal in a separate wire. This research is conducted to develop a reusable, scalable and configurable clockless version of SerDes system as the interconnect between multiple die. The proposed design achieves a data rate of 2 Gbps small area 38.71 μm² with architectural simplicity with 308 transistor count and low power consumption of 1.10 mW. 2016 Thesis http://eprints.usm.my/41312/ http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Chiew , Chong Giap Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
description	As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration of multiple die on a single chip. Communication between die requires full network-on-chip (NoC) which is area intensive. In deep sub-micron process nodes, high speed signaling between multiple die becomes one of the main challenges in multidie chip design. Methods to increase the routability have been proposed as the use of parallel interconnect appears to be the bottleneck of high speed multidie communication. Conversion of parallel data bits into serial data streams before transmission effectively reduced the number of wires required for the interconnect. Synchronous serial transmission requires large design dimension and power hungry auxiliary blocks for synchronization between the transmitted data and clock signals. This is avoided with the implementation of self-timed transmission scheme which eliminates the need to transmit the clock signal in a separate wire. This research is conducted to develop a reusable, scalable and configurable clockless version of SerDes system as the interconnect between multiple die. The proposed design achieves a data rate of 2 Gbps small area 38.71 μm² with architectural simplicity with 308 transistor count and low power consumption of 1.10 mW.
format	Thesis
qualification_level	Master's degree
author	Chiew , Chong Giap
author_facet	Chiew , Chong Giap
author_sort	Chiew , Chong Giap
title	Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
title_short	Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
title_full	Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
title_fullStr	Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
title_full_unstemmed	Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
title_sort	prelayout design of configurable serdes for high speed signaling in multidie interconnect
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2016
url	http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf
_version_	1747820908423151616

Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect

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