Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification

Sensors usage are becoming broader as the technology gets more advance in recent years, with its features becoming more sophisticated and can be found in wide range of products from cellphone to Internet of Thing (IoT). As a result, demand for new interface with more speed and bandwidth to transfer...

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Main Author:	Puan , Chia Kian
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41318/1/PUAN_CHIA_KIAN_24_Pages.pdf
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id	my-usm-ep.41318
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spelling	my-usm-ep.413182018-08-14T07:20:08Z Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification 2016 Puan , Chia Kian TK7800-8360 Electronics Sensors usage are becoming broader as the technology gets more advance in recent years, with its features becoming more sophisticated and can be found in wide range of products from cellphone to Internet of Thing (IoT). As a result, demand for new interface with more speed and bandwidth to transfer more data from sensor to the system for processing and existing communication will soon be surplus to the requirement to be able to transfer the large data fast enough to be processed. Hence, Improved Inter-Integrated Circuit (I3C) is introduced by Mobile Industry Processor Interface Alliance (MIPI) as new interface standard that able to deliver the required performance compared to its predecessor I2C, at the same time maintain the low power operation mode that’s essential to the sensor subsystem. As part of a new interface readiness, an Intel in-house I3C Test Card will be used in validation activity against the Controller in place of actual sensors or devices. While there is not any I3C controller based system available for testing yet, there is a need to have a temporary solution to replicate it in to enable the said I3C Test Card in order to have it ready once a system with I3C controller is available for validation. Thus, an I3C BFM is proposed to enable simple I3C protocol cycle transfers between it and I3C Test Card to achieve just that. I3C BFM will be FPGA based and capable to perform Enter Dynamic Address Assignment (ENTDAA) flow. The flow will require BFM to issue I3C Broadcast CCC and Modal Broadcast CCC protocol cycles. I3C Test Card will be assigned with a dynamic address upon completion of the flow and it is ready to send or receive I3C transaction as a result. 2016 Thesis http://eprints.usm.my/41318/ http://eprints.usm.my/41318/1/PUAN_CHIA_KIAN_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Puan , Chia Kian Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification
description	Sensors usage are becoming broader as the technology gets more advance in recent years, with its features becoming more sophisticated and can be found in wide range of products from cellphone to Internet of Thing (IoT). As a result, demand for new interface with more speed and bandwidth to transfer more data from sensor to the system for processing and existing communication will soon be surplus to the requirement to be able to transfer the large data fast enough to be processed. Hence, Improved Inter-Integrated Circuit (I3C) is introduced by Mobile Industry Processor Interface Alliance (MIPI) as new interface standard that able to deliver the required performance compared to its predecessor I2C, at the same time maintain the low power operation mode that’s essential to the sensor subsystem. As part of a new interface readiness, an Intel in-house I3C Test Card will be used in validation activity against the Controller in place of actual sensors or devices. While there is not any I3C controller based system available for testing yet, there is a need to have a temporary solution to replicate it in to enable the said I3C Test Card in order to have it ready once a system with I3C controller is available for validation. Thus, an I3C BFM is proposed to enable simple I3C protocol cycle transfers between it and I3C Test Card to achieve just that. I3C BFM will be FPGA based and capable to perform Enter Dynamic Address Assignment (ENTDAA) flow. The flow will require BFM to issue I3C Broadcast CCC and Modal Broadcast CCC protocol cycles. I3C Test Card will be assigned with a dynamic address upon completion of the flow and it is ready to send or receive I3C transaction as a result.
format	Thesis
qualification_level	Master's degree
author	Puan , Chia Kian
author_facet	Puan , Chia Kian
author_sort	Puan , Chia Kian
title	Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification
title_short	Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification
title_full	Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification
title_fullStr	Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification
title_full_unstemmed	Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification
title_sort	development of simple i3c controller bus functional modeling for internal test card verification
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2016
url	http://eprints.usm.my/41318/1/PUAN_CHIA_KIAN_24_Pages.pdf
_version_	1747820909882769408

Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification

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