20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement

In high-volume manufacturing (HVM), the degradations of signals at high speed and high frequencies will affect test results. In the semiconductor field, inaccuracies of test setup impact a product yield, increase test operating cost and delay products release time. With the demand for rapid improve...

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Main Author:	Shanmugam, Ragubalan
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41327/1/RAGUBALAN_AL_SHANMUGAM_24_Pages.pdf
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id	my-usm-ep.41327
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spelling	my-usm-ep.413272018-08-14T08:44:13Z 20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement 2015 Shanmugam, Ragubalan TK7800-8360 Electronics In high-volume manufacturing (HVM), the degradations of signals at high speed and high frequencies will affect test results. In the semiconductor field, inaccuracies of test setup impact a product yield, increase test operating cost and delay products release time. With the demand for rapid improvements in high-speed tests, signal integrity becomes very important. This thesis presents a 20-Gbps high-speed Converged I/O (CIO) and Peripherals Components Interference Express (PCIe) external loop back test design for signal integrity enhancement in a twenty six layer printed circuit board (PCB). The signal integrity effects were studied from the previous PCB design which operates at 5-Gbps at 2.5 GHz maximum operating frequency and the proposed PCB design were evaluated at 20-Gbps at 10 GHz maximum operating frequency. Several key design parameters such as different trace lengths were studied and components that were used in high-speed tests were further investigated from the previous PCB design. These efforts were performed to identify the dominating factors of signal integrity in high-speed test systems. In addition, research studies included the fabrication and measurement of test coupons to understand the impact of design parameters upon the completion of simulation prior to the actual PCB fabrication. In this thesis, the proposed PCB was tested at 20-Gbps and it was capable to operate with an insertion loss (IL) of - 4 dB. 2015 Thesis http://eprints.usm.my/41327/ http://eprints.usm.my/41327/1/RAGUBALAN_AL_SHANMUGAM_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Shanmugam, Ragubalan 20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement
description	In high-volume manufacturing (HVM), the degradations of signals at high speed and high frequencies will affect test results. In the semiconductor field, inaccuracies of test setup impact a product yield, increase test operating cost and delay products release time. With the demand for rapid improvements in high-speed tests, signal integrity becomes very important. This thesis presents a 20-Gbps high-speed Converged I/O (CIO) and Peripherals Components Interference Express (PCIe) external loop back test design for signal integrity enhancement in a twenty six layer printed circuit board (PCB). The signal integrity effects were studied from the previous PCB design which operates at 5-Gbps at 2.5 GHz maximum operating frequency and the proposed PCB design were evaluated at 20-Gbps at 10 GHz maximum operating frequency. Several key design parameters such as different trace lengths were studied and components that were used in high-speed tests were further investigated from the previous PCB design. These efforts were performed to identify the dominating factors of signal integrity in high-speed test systems. In addition, research studies included the fabrication and measurement of test coupons to understand the impact of design parameters upon the completion of simulation prior to the actual PCB fabrication. In this thesis, the proposed PCB was tested at 20-Gbps and it was capable to operate with an insertion loss (IL) of - 4 dB.
format	Thesis
qualification_level	Master's degree
author	Shanmugam, Ragubalan
author_facet	Shanmugam, Ragubalan
author_sort	Shanmugam, Ragubalan
title	20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement
title_short	20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement
title_full	20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement
title_fullStr	20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement
title_full_unstemmed	20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement
title_sort	20-gbps high-speed converged i/o loop back test design methodology for signal integrity enhancement
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2015
url	http://eprints.usm.my/41327/1/RAGUBALAN_AL_SHANMUGAM_24_Pages.pdf
_version_	1747820912078487552

20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement

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