Yusni, N. A. A. (2015). Technique Of Pvt Analysis On Sd Controller Timing Validation For 28nm Soc Fpga.
Chicago Style (17th ed.) CitationYusni, Nur Amalina Aiza. Technique Of Pvt Analysis On Sd Controller Timing Validation For 28nm Soc Fpga. 2015.
MLA引文Yusni, Nur Amalina Aiza. Technique Of Pvt Analysis On Sd Controller Timing Validation For 28nm Soc Fpga. 2015.
警告:這些引文格式不一定是100%准確.