Method For Validating The Integrity Of Clock Network Signal In Fpga Device
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Language: | English |
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2015
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Online Access: | http://eprints.usm.my/41500/1/MAYA_BINTI_ABU_BAKAR_24_Pages.pdf |
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my-usm-ep.415002018-08-24T07:09:47Z Method For Validating The Integrity Of Clock Network Signal In Fpga Device 2015 Bakar, Maya Abu TK7800-8360 Electronics 2015 Thesis http://eprints.usm.my/41500/ http://eprints.usm.my/41500/1/MAYA_BINTI_ABU_BAKAR_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik |
institution |
Universiti Sains Malaysia |
collection |
USM Institutional Repository |
language |
English |
topic |
TK7800-8360 Electronics |
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TK7800-8360 Electronics Bakar, Maya Abu Method For Validating The Integrity Of Clock Network Signal In Fpga Device |
description |
|
format |
Thesis |
qualification_level |
Master's degree |
author |
Bakar, Maya Abu |
author_facet |
Bakar, Maya Abu |
author_sort |
Bakar, Maya Abu |
title |
Method For Validating The Integrity Of Clock Network Signal In Fpga Device
|
title_short |
Method For Validating The Integrity Of Clock Network Signal In Fpga Device
|
title_full |
Method For Validating The Integrity Of Clock Network Signal In Fpga Device
|
title_fullStr |
Method For Validating The Integrity Of Clock Network Signal In Fpga Device
|
title_full_unstemmed |
Method For Validating The Integrity Of Clock Network Signal In Fpga Device
|
title_sort |
method for validating the integrity of clock network signal in fpga device |
granting_institution |
Universiti Sains Malaysia |
granting_department |
Pusat Pengajian Kejuruteraan Elektrik dan Elektronik |
publishDate |
2015 |
url |
http://eprints.usm.my/41500/1/MAYA_BINTI_ABU_BAKAR_24_Pages.pdf |
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1747820923294056448 |