Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform

Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs...

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Main Author: Hamza, Ekhlas Kadhum
Format: Thesis
Language:English
Published: 2011
Subjects:
Online Access:http://eprints.usm.my/43261/1/EKHLAS%20KADHUM%20HAMZA.pdf
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spelling my-usm-ep.432612019-04-12T05:26:29Z Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform 2011-10 Hamza, Ekhlas Kadhum TK1-9971 Electrical engineering. Electronics. Nuclear engineering Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. This thesis demonstrates a practical design and implementation procedure for building a useful, efficient and flexible model of a bit error rate tester (BERT) on physical layer for UHF-band of the digital transceivers by using new architecture in Multi-Core Software-Defined Radio 2011-10 Thesis http://eprints.usm.my/43261/ http://eprints.usm.my/43261/1/EKHLAS%20KADHUM%20HAMZA.pdf application/pdf en public phd doctoral Universiti Sains Malaysia Pusat Pengajian Kejuteraan Elektrik & Elektronik
institution Universiti Sains Malaysia
collection USM Institutional Repository
language English
topic TK1-9971 Electrical engineering
Electronics
Nuclear engineering
spellingShingle TK1-9971 Electrical engineering
Electronics
Nuclear engineering
Hamza, Ekhlas Kadhum
Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
description Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. This thesis demonstrates a practical design and implementation procedure for building a useful, efficient and flexible model of a bit error rate tester (BERT) on physical layer for UHF-band of the digital transceivers by using new architecture in Multi-Core Software-Defined Radio
format Thesis
qualification_name Doctor of Philosophy (PhD.)
qualification_level Doctorate
author Hamza, Ekhlas Kadhum
author_facet Hamza, Ekhlas Kadhum
author_sort Hamza, Ekhlas Kadhum
title Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_short Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_full Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_fullStr Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_full_unstemmed Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_sort development and implementation of a new technique for bert (bit error rate tester) using sdr platform
granting_institution Universiti Sains Malaysia
granting_department Pusat Pengajian Kejuteraan Elektrik & Elektronik
publishDate 2011
url http://eprints.usm.my/43261/1/EKHLAS%20KADHUM%20HAMZA.pdf
_version_ 1747821189031526400