Automated Placement Of A Transistor Pair For Analogue

The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focus...

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Main Author:	Balakrishnan, Saravanan
Format:	Thesis
Language:	English
Published:	2012
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/43926/1/Saravanan%20Balakrishnan24.pdf
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id	my-usm-ep.43926
record_format	uketd_dc
spelling	my-usm-ep.439262019-04-12T05:26:20Z Automated Placement Of A Transistor Pair For Analogue 2012-05 Balakrishnan, Saravanan TK1-9971 Electrical engineering. Electronics. Nuclear engineering The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint. 2012-05 Thesis http://eprints.usm.my/43926/ http://eprints.usm.my/43926/1/Saravanan%20Balakrishnan24.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Balakrishnan, Saravanan Automated Placement Of A Transistor Pair For Analogue
description	The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint.
format	Thesis
qualification_level	Master's degree
author	Balakrishnan, Saravanan
author_facet	Balakrishnan, Saravanan
author_sort	Balakrishnan, Saravanan
title	Automated Placement Of A Transistor Pair For Analogue
title_short	Automated Placement Of A Transistor Pair For Analogue
title_full	Automated Placement Of A Transistor Pair For Analogue
title_fullStr	Automated Placement Of A Transistor Pair For Analogue
title_full_unstemmed	Automated Placement Of A Transistor Pair For Analogue
title_sort	automated placement of a transistor pair for analogue
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik & Elektronik
publishDate	2012
url	http://eprints.usm.my/43926/1/Saravanan%20Balakrishnan24.pdf
_version_	1747821305495814144

Automated Placement Of A Transistor Pair For Analogue

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