Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits

The most important limitation in planer MOSFETs is current leakage between the source and the drain at the off-state (IOFF), which presents a critical problem in securing circuit reliability. To mitigate this problem, there are new types of transistors with a 3D structure, including silicon na...

Full description

Saved in:

Bibliographic Details
Main Author:	Naif, Yasir Hashim
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/45223/1/Yasir%20Hashim%20Naif24.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-usm-ep.45223
record_format	uketd_dc
spelling	my-usm-ep.452232019-08-07T07:43:56Z Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits 2013-07 Naif, Yasir Hashim TK1-9971 Electrical engineering. Electronics. Nuclear engineering The most important limitation in planer MOSFETs is current leakage between the source and the drain at the off-state (IOFF), which presents a critical problem in securing circuit reliability. To mitigate this problem, there are new types of transistors with a 3D structure, including silicon nanowire transistors (SiNWT). In order to optimize dimensions, ambient temperature and orientation of channel in SiNWT design, simulation is needed to characterize the behaviour of the SiNWT and help making design decisions. Over the last decade, there have been many researches focused on SiNWTs fabrication fields. However, these researches are all based on fabrication fields. Therefore, in this research, dimensions, ambient temperature and orientation of channel are modelled and taken into account to analyze performance improvement of SiNWT. Furthermore, in order to optimize dimensions, and logiclevel voltages of nanowire logic inverters circuits design, simulation is needed to characterize the limits of noise margins of the NW logic inverter and help making design decisions. There have been some proposed researches focused on NW logic inverters fabrication without focusing on optimization of logic levels and dimensions depending on noise margins as a limitation factor which represents a critical factor in the working of logic circuits performance, and this study is intended to be the first research to demonstrate dimensional optimization of nanowire logic inverter. This research contains two main parts, first part on the characterization of silicon nanowire transistor and the second on studying the characteristics of nanowire (NW) inverters. 2013-07 Thesis http://eprints.usm.my/45223/ http://eprints.usm.my/45223/1/Yasir%20Hashim%20Naif24.pdf application/pdf en public phd doctoral Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Naif, Yasir Hashim Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
description	The most important limitation in planer MOSFETs is current leakage between the source and the drain at the off-state (IOFF), which presents a critical problem in securing circuit reliability. To mitigate this problem, there are new types of transistors with a 3D structure, including silicon nanowire transistors (SiNWT). In order to optimize dimensions, ambient temperature and orientation of channel in SiNWT design, simulation is needed to characterize the behaviour of the SiNWT and help making design decisions. Over the last decade, there have been many researches focused on SiNWTs fabrication fields. However, these researches are all based on fabrication fields. Therefore, in this research, dimensions, ambient temperature and orientation of channel are modelled and taken into account to analyze performance improvement of SiNWT. Furthermore, in order to optimize dimensions, and logiclevel voltages of nanowire logic inverters circuits design, simulation is needed to characterize the limits of noise margins of the NW logic inverter and help making design decisions. There have been some proposed researches focused on NW logic inverters fabrication without focusing on optimization of logic levels and dimensions depending on noise margins as a limitation factor which represents a critical factor in the working of logic circuits performance, and this study is intended to be the first research to demonstrate dimensional optimization of nanowire logic inverter. This research contains two main parts, first part on the characterization of silicon nanowire transistor and the second on studying the characteristics of nanowire (NW) inverters.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Naif, Yasir Hashim
author_facet	Naif, Yasir Hashim
author_sort	Naif, Yasir Hashim
title	Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
title_short	Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
title_full	Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
title_fullStr	Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
title_full_unstemmed	Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
title_sort	design and characterization of silicon nanowire transistor and logic nanowire inverter circuits
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik & Elektronik
publishDate	2013
url	http://eprints.usm.my/45223/1/Yasir%20Hashim%20Naif24.pdf
_version_	1747821472488882176

Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits

Similar Items