Accelerated Verilog Simulator Using Application Specific Microprocessor
Logic simulation is an important step in Very Large Scale Integration (VLSI) IC development. Advancement in Hardware Description Language (HDL) has made Verilog a widely adopted language used to model digital circuit and verification test bench. Electronic Design Automation (EDA) vendor provides...
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my-usm-ep.457882021-11-17T03:42:16Z Accelerated Verilog Simulator Using Application Specific Microprocessor 2017-05 Tan Tze Sin, Tze Sin T Technology TK Electrical Engineering. Electronics. Nuclear Engineering Logic simulation is an important step in Very Large Scale Integration (VLSI) IC development. Advancement in Hardware Description Language (HDL) has made Verilog a widely adopted language used to model digital circuit and verification test bench. Electronic Design Automation (EDA) vendor provides software and hardwareassisted approaches to carry out simulations. However, software-based simulator is slow whereas hardware-assisted simulator does not offer the same simulation fidelity stipulated in Verilog. In this research project, a hardware-assisted Verilog simulator, VerCPU System, was proposed to address shortcomings in existing platforms. The simulator core is a custom designed application specific microprocessor specifically adapted to handle Verilog simulation. The microprocessor computes Verilog data in its native form while supporting event-driven parallelism directly to achieve speed supremacy. Being a compiled-code simulator, simulation fidelity compliancy is retained to offer the same result and visibility like the software-based solution. A functional system, VerCPU, was developed and prototyped on a Field Programmable Gate Array (FPGA) development board. This system was successfully verified and benchmarked against a software-based compiled-code simulator, i.e. Synopsys VCS®. VerCPU System can already achieve up to 6 times speed superiority with basic speed improvement techniques applied. The simulator had proven to be a viable alternate Verilog simulator to meet future simulation needs. 2017-05 Thesis http://eprints.usm.my/45788/ http://eprints.usm.my/45788/1/Accelerated%20Verilog%20Simulator%20Using%20Application%20Specific%20Microprocessor.pdf application/pdf en public phd doctoral Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik & Elektronik |
| institution |
Universiti Sains Malaysia |
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USM Institutional Repository |
| language |
English |
| topic |
T Technology T Technology |
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T Technology T Technology Tan Tze Sin, Tze Sin Accelerated Verilog Simulator Using Application Specific Microprocessor |
| description |
Logic simulation is an important step in Very Large Scale Integration (VLSI)
IC development. Advancement in Hardware Description Language (HDL) has made
Verilog a widely adopted language used to model digital circuit and verification test
bench. Electronic Design Automation (EDA) vendor provides software and hardwareassisted
approaches to carry out simulations. However, software-based simulator is
slow whereas hardware-assisted simulator does not offer the same simulation fidelity
stipulated in Verilog. In this research project, a hardware-assisted Verilog simulator,
VerCPU System, was proposed to address shortcomings in existing platforms. The
simulator core is a custom designed application specific microprocessor specifically
adapted to handle Verilog simulation. The microprocessor computes Verilog data in
its native form while supporting event-driven parallelism directly to achieve speed
supremacy. Being a compiled-code simulator, simulation fidelity compliancy is
retained to offer the same result and visibility like the software-based solution. A
functional system, VerCPU, was developed and prototyped on a Field Programmable
Gate Array (FPGA) development board. This system was successfully verified and
benchmarked against a software-based compiled-code simulator, i.e. Synopsys VCS®.
VerCPU System can already achieve up to 6 times speed superiority with basic speed
improvement techniques applied. The simulator had proven to be a viable alternate
Verilog simulator to meet future simulation needs. |
| format |
Thesis |
| qualification_name |
Doctor of Philosophy (PhD.) |
| qualification_level |
Doctorate |
| author |
Tan Tze Sin, Tze Sin |
| author_facet |
Tan Tze Sin, Tze Sin |
| author_sort |
Tan Tze Sin, Tze Sin |
| title |
Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_short |
Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_full |
Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_fullStr |
Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_full_unstemmed |
Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_sort |
accelerated verilog simulator using application specific microprocessor |
| granting_institution |
Universiti Sains Malaysia |
| granting_department |
Pusat Pengajian Kejuruteraan Elektrik & Elektronik |
| publishDate |
2017 |
| url |
http://eprints.usm.my/45788/1/Accelerated%20Verilog%20Simulator%20Using%20Application%20Specific%20Microprocessor.pdf |
| _version_ |
1747821566368940032 |