Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
Through-silicon via (TSV) technology has been an emerging technology to 3D heterogeneous system integration through vertical interconnection. This promising technology enables smaller footprints, reduced signal delay, shorter interconnections, lower power consumption and higher integration densit...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://eprints.usm.my/61078/1/24%20Pages%20from%20Pages%20from%2000001780128.pdf |
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| Summary: | Through-silicon via (TSV) technology has been an emerging technology to
3D heterogeneous system integration through vertical interconnection. This
promising technology enables smaller footprints, reduced signal delay, shorter
interconnections, lower power consumption and higher integration density as
compared to the existing 2D planar system integration and 3D IC with wire bonds.
Despite all the benefits, there are still many challenges ahead for this technology to
be both technically and economically viable. Plastic encapsulation process is one of
the critical challenges in the continual shrinking of TSV diameter, wafer thickness
and microbump pitch. In this thesis, both experimental and numerical approaches are
used to study the plastic encapsulation process in 3D IC package with TSV. The
objectives of this research include establishing feasible methods to analyze flow front
advancement, pressure distribution, velocity profile and curing rate of epoxy molding
compound during encapsulation process. |
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