Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology

Through-silicon via (TSV) technology has been an emerging technology to 3D heterogeneous system integration through vertical interconnection. This promising technology enables smaller footprints, reduced signal delay, shorter interconnections, lower power consumption and higher integration densit...

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Main Author:	Ong, Ern Seang
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/61078/1/24%20Pages%20from%20Pages%20from%2000001780128.pdf
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id	my-usm-ep.61078
record_format	uketd_dc
spelling	my-usm-ep.610782024-09-10T02:39:47Z Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology 2013-02 Ong, Ern Seang TK1-9971 Electrical engineering. Electronics. Nuclear engineering Through-silicon via (TSV) technology has been an emerging technology to 3D heterogeneous system integration through vertical interconnection. This promising technology enables smaller footprints, reduced signal delay, shorter interconnections, lower power consumption and higher integration density as compared to the existing 2D planar system integration and 3D IC with wire bonds. Despite all the benefits, there are still many challenges ahead for this technology to be both technically and economically viable. Plastic encapsulation process is one of the critical challenges in the continual shrinking of TSV diameter, wafer thickness and microbump pitch. In this thesis, both experimental and numerical approaches are used to study the plastic encapsulation process in 3D IC package with TSV. The objectives of this research include establishing feasible methods to analyze flow front advancement, pressure distribution, velocity profile and curing rate of epoxy molding compound during encapsulation process. 2013-02 Thesis http://eprints.usm.my/61078/ http://eprints.usm.my/61078/1/24%20Pages%20from%20Pages%20from%2000001780128.pdf application/pdf en public masters Perpustakaan Hamzah Sendut Pusat Pengajian Kejuruteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Ong, Ern Seang Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
description	Through-silicon via (TSV) technology has been an emerging technology to 3D heterogeneous system integration through vertical interconnection. This promising technology enables smaller footprints, reduced signal delay, shorter interconnections, lower power consumption and higher integration density as compared to the existing 2D planar system integration and 3D IC with wire bonds. Despite all the benefits, there are still many challenges ahead for this technology to be both technically and economically viable. Plastic encapsulation process is one of the critical challenges in the continual shrinking of TSV diameter, wafer thickness and microbump pitch. In this thesis, both experimental and numerical approaches are used to study the plastic encapsulation process in 3D IC package with TSV. The objectives of this research include establishing feasible methods to analyze flow front advancement, pressure distribution, velocity profile and curing rate of epoxy molding compound during encapsulation process.
format	Thesis
qualification_level	Master's degree
author	Ong, Ern Seang
author_facet	Ong, Ern Seang
author_sort	Ong, Ern Seang
title	Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
title_short	Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
title_full	Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
title_fullStr	Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
title_full_unstemmed	Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
title_sort	analysis of plastic encapsulation process in 3d ic package with through-silicon via (tsv) technology
granting_institution	Perpustakaan Hamzah Sendut
granting_department	Pusat Pengajian Kejuruteraan Elektrik & Elektronik
publishDate	2013
url	http://eprints.usm.my/61078/1/24%20Pages%20from%20Pages%20from%2000001780128.pdf
_version_	1811772874977968128

Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology

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