Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory

Resistive Random-Access Memory (ReRAM) is one of the potential candidates of emerging semiconductor memory to replace the conventional memory technologies.Besides, ReRAM offers many attractive advantages, such as non-volatile, scalable, low power consumption, and fast data access. Due to the infancy...

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Main Author:	Arshad, Norsuhaidah
Format:	Thesis
Language:	English English
Published:	2016
Subjects:	T Technology (General)
Online Access:	http://eprints.utem.edu.my/id/eprint/18373/1/Fault%20Analysis%20And%20Test%20For%20Bridge%20Defect%20In%20Resistive%20Random%20Access%20Memory.pdf http://eprints.utem.edu.my/id/eprint/18373/2/Fault%20Analysis%20And%20Test%20For%20Bridge%20Defect%20In%20Resistive%20Random%20Access%20Memory.pdf
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institution	Universiti Teknikal Malaysia Melaka
collection	UTeM Repository
language	English English
topic	T Technology (General) T Technology (General)
spellingShingle	T Technology (General) T Technology (General) Arshad, Norsuhaidah Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory
description	Resistive Random-Access Memory (ReRAM) is one of the potential candidates of emerging semiconductor memory to replace the conventional memory technologies.Besides, ReRAM offers many attractive advantages, such as non-volatile, scalable, low power consumption, and fast data access. Due to the infancy stage of this emerging memory, ReRAM is prone to have bridge defects that could lead to test escape and reliability issues. Moreover, with the lack of electrical model for ReRAM, this research presents an electrical ReRAM model that was designed with SILVACO Electronic Design Automation (EDA) software. All ReRAM elements designed used 22nm Complementary Metal Oxide Semiconductor (CMOS) transistors and a novel non- CMOS device, known as memristor, as the memory cell array. The optimal memristor model that had been proposed by D. Biolek was chosen among three published memristor SPICE models. The selection was made based on the performance analysis.Furthermore, simulation of 2x2 cell ReRAM was executed in order to prove the functionality of the design. The designed ReRAM model functioned as desired based on the simulation results. In addition, the defective behaviors of the faulty ReRAM that were impacted by the three types of bridge defects, (bridge between wordlines; BW, bridge between bitlines; BB and bridge between bitlines and wordlines; BBW) had been studied in this work. The faulty ReRAM model was established by injecting the defects into the designed electrical ReRAM model. As this ReRAM employed a non-CMOS device as its memory cells, the defect that occurred might behave differently than that happens in conventional memories. This could cause the faulty ReRAM to escape from the available memory test. The simulation of the faulty ReRAM model showed that the bridge defects had been due to the Undefined State Faults (USFs) during reading operation. Besides, any faulty in ReRAM caused by USF makes setting the cell to the desired logical value a challenging task, and this fault is difficult to be detected. Hence, a new Design-for-Testability (DfT) technique was proposed to detect these USFs. This technique, known as Adaptive Sensing Read Voltage (ASRV), had been developed based on the mechanism of memristor, as well as the function of sense amplifier. Apart from that, a slight circuit modification was done to implement the DfT circuitry. Based on the simulation results during the DfT implementation, the proposed DfT technique successfully detects the USFs that occurred when 0Ω ≤ RBW ≤ 50Ω for BW injection, 36Ω ≤ RBB ≤ 372Ω for BB injection and 140Ω ≤ RBBW ≤ 210Ω for BBW injection.However, this DfT technique might not suitable for BBW injection as it might kill the healthy cell.
format	Thesis
qualification_name	Master of Philosophy (M.Phil.)
qualification_level	Master's degree
author	Arshad, Norsuhaidah
author_facet	Arshad, Norsuhaidah
author_sort	Arshad, Norsuhaidah
title	Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory
title_short	Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory
title_full	Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory
title_fullStr	Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory
title_full_unstemmed	Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory
title_sort	fault analysis and test for bridge defect in resistive random access memory
granting_institution	Universiti Teknikal Malaysia Melaka
granting_department	Faculty of Electronic and Computer Engineering
publishDate	2016
url	http://eprints.utem.edu.my/id/eprint/18373/1/Fault%20Analysis%20And%20Test%20For%20Bridge%20Defect%20In%20Resistive%20Random%20Access%20Memory.pdf http://eprints.utem.edu.my/id/eprint/18373/2/Fault%20Analysis%20And%20Test%20For%20Bridge%20Defect%20In%20Resistive%20Random%20Access%20Memory.pdf
_version_	1747833925395283968
spelling	my-utem-ep.183732021-10-08T13:00:42Z Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory 2016 Arshad, Norsuhaidah T Technology (General) TK Electrical engineering. Electronics Nuclear engineering Resistive Random-Access Memory (ReRAM) is one of the potential candidates of emerging semiconductor memory to replace the conventional memory technologies.Besides, ReRAM offers many attractive advantages, such as non-volatile, scalable, low power consumption, and fast data access. Due to the infancy stage of this emerging memory, ReRAM is prone to have bridge defects that could lead to test escape and reliability issues. Moreover, with the lack of electrical model for ReRAM, this research presents an electrical ReRAM model that was designed with SILVACO Electronic Design Automation (EDA) software. All ReRAM elements designed used 22nm Complementary Metal Oxide Semiconductor (CMOS) transistors and a novel non- CMOS device, known as memristor, as the memory cell array. The optimal memristor model that had been proposed by D. Biolek was chosen among three published memristor SPICE models. The selection was made based on the performance analysis.Furthermore, simulation of 2x2 cell ReRAM was executed in order to prove the functionality of the design. The designed ReRAM model functioned as desired based on the simulation results. In addition, the defective behaviors of the faulty ReRAM that were impacted by the three types of bridge defects, (bridge between wordlines; BW, bridge between bitlines; BB and bridge between bitlines and wordlines; BBW) had been studied in this work. The faulty ReRAM model was established by injecting the defects into the designed electrical ReRAM model. As this ReRAM employed a non-CMOS device as its memory cells, the defect that occurred might behave differently than that happens in conventional memories. This could cause the faulty ReRAM to escape from the available memory test. The simulation of the faulty ReRAM model showed that the bridge defects had been due to the Undefined State Faults (USFs) during reading operation. Besides, any faulty in ReRAM caused by USF makes setting the cell to the desired logical value a challenging task, and this fault is difficult to be detected. Hence, a new Design-for-Testability (DfT) technique was proposed to detect these USFs. This technique, known as Adaptive Sensing Read Voltage (ASRV), had been developed based on the mechanism of memristor, as well as the function of sense amplifier. Apart from that, a slight circuit modification was done to implement the DfT circuitry. Based on the simulation results during the DfT implementation, the proposed DfT technique successfully detects the USFs that occurred when 0Ω ≤ RBW ≤ 50Ω for BW injection, 36Ω ≤ RBB ≤ 372Ω for BB injection and 140Ω ≤ RBBW ≤ 210Ω for BBW injection.However, this DfT technique might not suitable for BBW injection as it might kill the healthy cell. 2016 Thesis http://eprints.utem.edu.my/id/eprint/18373/ http://eprints.utem.edu.my/id/eprint/18373/1/Fault%20Analysis%20And%20Test%20For%20Bridge%20Defect%20In%20Resistive%20Random%20Access%20Memory.pdf text en public http://eprints.utem.edu.my/id/eprint/18373/2/Fault%20Analysis%20And%20Test%20For%20Bridge%20Defect%20In%20Resistive%20Random%20Access%20Memory.pdf text en validuser https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=100175 mphil masters Universiti Teknikal Malaysia Melaka Faculty of Electronic and Computer Engineering 1. Adams, R.D., 2002. Memory Faults. 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Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory

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