Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller

Smart microgrids have emerged as a viable solution in case of emergency situations occurred at the main electricity grid. The main concern of a smart microgrid is the degradation of the power quality caused by harmonic distortion originated from the non-linear equipment. With the rapid development o...

Full description

Saved in:

Bibliographic Details
Main Author:	Salim, Sani Irwan
Format:	Thesis
Language:	English English
Published:	2018
Subjects:	T Technology (General)
Online Access:	http://eprints.utem.edu.my/id/eprint/23316/1/Optimized%20Fast%20Fourier%20Transform%20Architecture%20Using%20Instruction%20Set%20Architecture%20Extension%20In%20Low-End%20Digital%20Signal%20Controller.pdf http://eprints.utem.edu.my/id/eprint/23316/2/Optimized%20Fast%20Fourier%20Transform%20Architecture%20Using%20Instruction%20Set%20Architecture%20Extension%20In%20Low-End%20Digital%20Signal%20Controller.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-utem-ep.23316
record_format	uketd_dc
institution	Universiti Teknikal Malaysia Melaka
collection	UTeM Repository
language	English English
topic	T Technology (General) T Technology (General)
spellingShingle	T Technology (General) T Technology (General) Salim, Sani Irwan Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller
description	Smart microgrids have emerged as a viable solution in case of emergency situations occurred at the main electricity grid. The main concern of a smart microgrid is the degradation of the power quality caused by harmonic distortion originated from the non-linear equipment. With the rapid development of power electronic technology, the increased of harmonic-producing loads in the smart microgrids necessitating a new digital signal controller architecture for the harmonic measurement system. While the current system configurations are directed towards the 32-bit architecture, it shows higher requirements in area footprint and multi-core setup. This thesis presents the design of a low-end digital signal controller architecture using instruction set architecture (ISA) extension for the implementation of the harmonic measurement system in a smart microgrid. A new architecture, called UTeMRISC, is developed from the baseline 8-bit microcontroller with the capability to perform signal processing applications such as Fast Fourier Transform (FFT). The architecture is improved using the Application-Specific Instruction Set Processor (ASIP) approach by extending the instruction set architecture to 16-bit length. Instruction set customization is implemented to enable the execution of computationally intensive tasks. The entire architecture is described in Verilog Hardware Description Language (HDL) and implemented on the Virtex-6 FPGA board. From the test programs, UTeMRISC has demonstrated faster execution times and higher maximum operating frequency while not significantly increased the core’s resource utilization. Compared to the initial processor architecture, the support of extended ISA has increased the UTeMRISC core by 21.8% but at the same time allows to execute Fast Fourier Transform algorithm up to 5× faster. The combine effort of ISA extension and optimized instruction set generation results in up to 1 Mega sample per second, which translated to 66.8% increase of data throughput in the FFT algorithm when compared to a 32-bit architecture. This research proves that with comprehensive ASIP methodology and ISA extension, a low-end digital signal controller architecture is feasible and effective to be implemented in a harmonic measurement system for a smart microgrid.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Salim, Sani Irwan
author_facet	Salim, Sani Irwan
author_sort	Salim, Sani Irwan
title	Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller
title_short	Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller
title_full	Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller
title_fullStr	Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller
title_full_unstemmed	Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller
title_sort	optimized fast fourier transform architecture using instruction set architecture extension in low-end digital signal controller
granting_institution	Universiti Teknikal Malaysia Melaka
granting_department	Faculty Of Electronic And Computer Engineering
publishDate	2018
url	http://eprints.utem.edu.my/id/eprint/23316/1/Optimized%20Fast%20Fourier%20Transform%20Architecture%20Using%20Instruction%20Set%20Architecture%20Extension%20In%20Low-End%20Digital%20Signal%20Controller.pdf http://eprints.utem.edu.my/id/eprint/23316/2/Optimized%20Fast%20Fourier%20Transform%20Architecture%20Using%20Instruction%20Set%20Architecture%20Extension%20In%20Low-End%20Digital%20Signal%20Controller.pdf
_version_	1747834034128420864
spelling	my-utem-ep.233162022-03-15T09:31:57Z Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller 2018 Salim, Sani Irwan T Technology (General) TK Electrical engineering. Electronics Nuclear engineering Smart microgrids have emerged as a viable solution in case of emergency situations occurred at the main electricity grid. The main concern of a smart microgrid is the degradation of the power quality caused by harmonic distortion originated from the non-linear equipment. With the rapid development of power electronic technology, the increased of harmonic-producing loads in the smart microgrids necessitating a new digital signal controller architecture for the harmonic measurement system. While the current system configurations are directed towards the 32-bit architecture, it shows higher requirements in area footprint and multi-core setup. This thesis presents the design of a low-end digital signal controller architecture using instruction set architecture (ISA) extension for the implementation of the harmonic measurement system in a smart microgrid. A new architecture, called UTeMRISC, is developed from the baseline 8-bit microcontroller with the capability to perform signal processing applications such as Fast Fourier Transform (FFT). The architecture is improved using the Application-Specific Instruction Set Processor (ASIP) approach by extending the instruction set architecture to 16-bit length. Instruction set customization is implemented to enable the execution of computationally intensive tasks. The entire architecture is described in Verilog Hardware Description Language (HDL) and implemented on the Virtex-6 FPGA board. From the test programs, UTeMRISC has demonstrated faster execution times and higher maximum operating frequency while not significantly increased the core’s resource utilization. Compared to the initial processor architecture, the support of extended ISA has increased the UTeMRISC core by 21.8% but at the same time allows to execute Fast Fourier Transform algorithm up to 5× faster. The combine effort of ISA extension and optimized instruction set generation results in up to 1 Mega sample per second, which translated to 66.8% increase of data throughput in the FFT algorithm when compared to a 32-bit architecture. This research proves that with comprehensive ASIP methodology and ISA extension, a low-end digital signal controller architecture is feasible and effective to be implemented in a harmonic measurement system for a smart microgrid. 2018 Thesis http://eprints.utem.edu.my/id/eprint/23316/ http://eprints.utem.edu.my/id/eprint/23316/1/Optimized%20Fast%20Fourier%20Transform%20Architecture%20Using%20Instruction%20Set%20Architecture%20Extension%20In%20Low-End%20Digital%20Signal%20Controller.pdf text en public http://eprints.utem.edu.my/id/eprint/23316/2/Optimized%20Fast%20Fourier%20Transform%20Architecture%20Using%20Instruction%20Set%20Architecture%20Extension%20In%20Low-End%20Digital%20Signal%20Controller.pdf text en validuser http://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=112319 phd doctoral Universiti Teknikal Malaysia Melaka Faculty Of Electronic And Computer Engineering 1. Almasri, I., Abandah, G., Shhadeh, A. & Shahrour, A. 2011. Universal ISA Simulator with Soft Processor FPGA Implementation. IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT), pp. 1-6. 2. Aneesh, R. & Jiju, K., 2012. Design of FPGA based 8-bit RISC controller IP core using VHDL, Annual IEEE India Conference (INDICON), pp. 427-432. 3. Aspalli, M., Munshi, F. M. & Medegar, S. L., 2015. Speed Control of BLDC Motor with Four Switch Three Phase Inverter Using Digital Signal Controller. 2015 International Conference on IEEE Power and Advanced Control Engineering (ICPACE), pp. 371-376. 4. Ball, J., 2007. Designing Soft-Core Processors for FPGAs Processor Design. In: Nurmi, J. (ed.) Processor Design: System-on-Chip Computing for ASICs and FPGAs. 1st ed. Springer Netherlands. 5. Bannatyne, R., 2003. Hybrid Digital Signal Controller Enables Next Generation Automotive Control System. Embedded Computing Design [Online]. Available: http://embedded-computing.com/pdfs/Motorola.Win03.pdf [Accessed 1 July 2013]. 6. Barat, F. & Lauwereins, R., 2000. Reconfigurable Instruction set Processors: A Survey. Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype, pp. 168-173. 7. Bo, J. & Jinhui, W., 2016. Research on harmonic Analysis Of Low Voltage Distribution Networks And Its Monitoring System. IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC), pp. 1416-1420. 8. Bourogaoui, M., Sethom, H. B. A. & Belkhodja, I. S., 2015. Real-time encoder Faults Detection And Rotor Position Estimation For Permanent Magnet Synchronous Motor Drives Fault Tolerant Sensorless Control Using Digital Signal Controller. Mathematics and Computers in Simulation, 131, pp. 253-267.157 9. Brandner, F., Ebner, D. & Krall, A., 2007. Compiler generation From Structural Architecture Descriptions. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 13-22. 10. Brandner, F., Horspool, N. & Krall, A., 2010. DSP Instruction Set Simulation. In: Bhattacharyya, S. S., Deprettere, E. F., Leupers, R. & Takala, J. (eds.) Handbook of Signal Processing Systems. 1st ed.: Springer US. 11. Celio, C., Chiu, P.-F., Nikolić, B., Patterson, D. A. & Asanović, K., 2017. BOOMv2: an Open-Source Out-of-Order RISC-V Core. First Workshop on Computer Architecture Research with RISC-V (CARRV). pp. 1-6. 12. Chan, W. K., Tseng, Y. H., Lin, Y. S. & Chien, S. Y., 2014. Coarse-grained Reconfigurable Stream Processor For Distributed Smart Cameras. 2014 IEEE Workshop on Signal Processing Systems (SiPS), pp. 1-6. 13. Conrad, J. M. & Dean, A. G., 2011. Embedded Systems, An Introduction Using the Renesas RX62N Microcontroller, Micrium Press. 14. Cooley, J. W. & Tukey, J. W., 1965. An Algorithm For The Machine Calculation Of Complex Fourier Series. Mathematics of Computation, 19, pp. 297-301. 15. Coonan, T., 1999. RISC8 Verilog Core [Online]. Available: http://pldworld.info/_hdl/2/_ip/mindspring/~tcoonan/risc8doc.html [Accessed 4 January 2017]. 16. Cooper, K. & Torczon, L., 2011. Engineering a Compiler, Morgan Kaufmann. Datta, A., Mukherjee, D. & Saha, H., 2014. A dsPIC Based Novel Digital Sinusoidal Pulse-Width Modulation Technique For Voltage Source Inverter Applications. Microprocessors and Microsystems, 38, pp. 649-658.158 17. Deng, C., Liu, L., Li, Z., Yin, S. & Wei, S., 2014. Teach Reconfigurable Computing Using Mixed-Grained Fabrics Based Hardware Infrastructure. 2014 IEEE Frontiers in Education Conference (FIE) Proceedings, pp. 1-9. 18. Donovan, J., 2014. Is There a Future for 8-Bit MCUs? [Online]. Available: http://www.digikey.com/en/articles/techzone/2014/feb/is-there-a-future-for-8-bit-mcus [Accessed 2 July 2014]. 19. Durdhavale, S. R. & Ahire, D. D., 2016. A Review of Harmonics Detection and Measurement in Power System. International Journal of Computer Applications, 143, pp. 42-45. EEMBC, 2016. Multicore Benchmark Software. 20. Farhangi, H., 2010. The path of the smart grid. IEEE Power and Energy Magazine, 8, pp. 18-28. 21. Gadre, D., 2007. Programming and customizing the AVR microcontroller, McGrawHill/TAB Electronics. 22. Gaisler, J., 2002. A Portable and Fault-Tolerant Microprocessor Based on The SPARC v8 Architecture. Proceedings. International Conference on Dependable Systems and Networks, IEEE, pp. 409-415. 23. Galuzzi, C. & Bertels, K., 2011. The Instruction-Set Extension Problem: A Survey. ACM Trans Reconfigurable Technol. Syst., 4, pp. 1-28. 24. Ganssle, J., 2012. Is 8-bits dying? [Online]. Available: http://www.embedded.com/electronics-blogs/break-points/4389890/Is-8-bits-dying- [Accessed 2 July 2014].159 25. Gautschi, M., Traber, A., Pullini, A., Benini, L., Scandale, M., Di Federico, A., Beretta, M. & Agosta, G., 2015. Tailoring Instruction-Set Extensions for an Ultra-Low Power TightlyCoupled Cluster of OpenRISC Cores. 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 25-30. 26. Ghica, L., Ditu, B. & Tapus, N., 2013. Automatic Generation of Architecture Model for Reconfigurable Build Tools. 19th International Conference on Control Systems and Computer Science (CSCS), IEEE, pp. 142-146. 27. Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T. & Brown, R. B., 2001. MiBench: A Free, Commercially Representative Embedded Benchmark Suite. 2001 IEEE International Workshop on Workload Characterization, IEEE, pp. 3-14. 28. Hajduk, Z., 2014. An FPGA Embedded Microcontroller. Microprocessors and Microsystems, 38, pp. 1-8. 29. Hare, J., Shi, X., Gupta, S. & Bazzi, A., 2016. Fault Diagnostics in Smart Micro-grids: A survey. Renewable and Sustainable Energy Reviews, 60, pp. 1114-1124. 30. Hassan, H., Mohammed, K. & Shalash, A., 2012. Implementation of a Reconfigurable ASIP for High Throughput Low Power DFT/DCT/FIR Engine. EURASIP Journal on Embedded Systems, 2012, pp. 1-18. 31. Hennessy, J. L. & Patterson, D. A., 2011. Computer Architecture: A Quantitative Approach, Elsevier. 32. Hessabi, S., Modarressi, M., Goudarzi, M. & Javanhemmat, H., 2006. A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 7-13.160 33. Hoffmann, A. & Nohl, A., 2006. The Dusk of ASIC the Dawn of ASIP [Online]. CoWare Inc. Available: http://www.techonline.com/electrical-engineers/education-training/techpapers/4125807/The-dusk-of-ASIC-the-dawn-of-ASIP [Accessed 2 July 2014]. 34. Hong, Y., Ming-Che, L., Kui, D. & Zhi-Ying, W., 2005. Design of a Configurable Embedded Processor Architecture for DSP Functions. 11th International Conference on Parallel and Distributed Systems, pp. 27-31. 35. Ienne, P. & Leupers, R., 2006. Customizable Embedded Processors: Design Technologies and Applications, Academic Press. 36. Iqbal, S. M. Z., Liang, Y. & Grahn, H., 2010. Parmibench-An Open-Source Benchmark for Embedded Multiprocessor Systems. IEEE Computer Architecture Letters, 9, pp. 45-48. 37. Jain, M. K., Balakrishnan, M. & Kumar, A., 2001. ASIP Design Methodologies: Survey and Issues. Fourteenth International Conference on.VLSI Design, pp. 76-81. 38. Jeemon, J., 2015. Low Power Pipelined 8-bit RISC Processor Design and Implementation on FPGA. International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), IEEE, pp. 476-481. 39. Jo, J., Han, B.-M. & Cha, H., 2015. FPGA based DSC-PLL for Grid Harmonics and Voltage Unbalance Effect Elimination. 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), IEEE, pp. 2212-2216. 40. Kalair, A., Abas, N., Kalair, A., Saleem, Z. & Khan, N., 2017. Review of Harmonic Analysis, Modeling and Mitigation Techniques. Renewable and Sustainable Energy Reviews, 78, pp. 1152-1187. 41. Karuri, K., Chattopadhyay, A., Chen, X., Kammler, D., Hao, L., Leupers, R., Meyr, H. & Ascheid, G., 2008. A Design Flow for Architecture Exploration and Implementation of161 Partially Reconfigurable Processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16, pp. 1281-1294. 42. Kazmierkowski, M. P., Jasinski, M. & Wrona, G., 2011. DSP-based Control of GridConnected Power Converters Operating Under Grid Distortions. IEEE Transactions on Industrial Informatics, 7, pp. 204-211. 43. Khan, M., Radwan, T. S. & Rahman, M. A., 2007. Real-time Implementation of Wavelet Packet Transform-Based Diagnosis and Protection of Three-Phase Induction Motors. IEEE Transactions on Energy Conversion, 22, pp. 647-655. 44. Kim, D.-H., 2014. Addressing Mode Extension to the ARM/THUMB Architecture. Advances in Electrical and Computer Engineering, 14, pp. 85-88. 45. Kim, T. & Hoskote, Y., 2014. Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism. 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6. 46. Kissell, K., 1997. MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group. 47. Ko, K., 2012. ADL-Driven Simulator Generation for Energy Dissipation Tracing and Monitoring. In: J. Park, J., Leung, V. C. M., Wang, C.-L. & Shon, T. (eds.) Future Information Technology, Application, and Service. Springer Netherlands. 48. Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H. 2014. Design and evaluation of fine-grained power-gating for embedded microprocessors. 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6.162 49. Kovács, M. & Kollár, Z. 2017. Software Implementation of the Recursive Discrete Fourier Transform. 27th International Conference Radioelektronika (RADIOELEKTRONIKA), IEEE, pp. 1-5. 50. Krishnan, N. R. & Sivasuparamanyan, K., 2013. A Reconfigurable Low Power FPGA Design with Autonomous Power Gating and LEDR Encoding. 7th International Conference on Intelligent Systems and Control (ISCO), pp. 221-226. 51. Lampret, D. & Baxter, J., 2014. OpenRISC 1200 IP Core Specification (Preliminary Draft). 52. Lattice Semiconductor, C., 2007. Lattice Mico8 Open, Free Soft Microcontroller [Online]. Available: http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/I PCores02/Mico8.aspx [Accessed 2018]. 53. Li, Y., Zhu, X., Zhang, W., Wang, C. & Deng, Z., 2013. Research and Design of CPU for Teaching Based on SPARC V8. Journal of Theoretical and Applied Information Technology, 50, pp. 352-357. 54. Liu, D., 2008. Embedded DSP Processor Design, : Application Specific Instruction Set Processors, Morgan Kaufmann. 55. Lopes, B. C., Ecco, L., Xavier, E. C. & Azevedo, R., 2016. Design and Evaluation of Compact ISA Extensions. Microprocessors and Microsystems, 40, pp. 1-15. 56. Lozano, H. & Ito, M. 2015. A Reduced Complexity Instruction Set Architecture for Low Cost Embedded Processors. International Conference on High Performance Computing & Simulation (HPCS), pp. 400-407.163 57. Mansoor, A. Z., Khalil, M. R. & Jasim, O. A., 2011. Position Control of DC Servo Motors Using Soft-Core Processor on FPGA to Move Robot Arm. Journal of Theoretical and Applied Information Technology, 32, pp. 99-106. 58. Melo, C. A. R. & Barros, E., 2016. Oolong: A Baseband Processor Extension to the RISCV ISA. 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), IEEE, pp. 241-242. 59. Mentzer, N., Payá-Vayá, G., Blume, H., Egloffstein, N. V. & Ritter, W. 2014. InstructionSet Extension for an ASIP-Based SIFT Feature Extraction. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp. 335-342. 60. Metrolho, J. C., Silva, C. A., Couto, C. & Tavares, A., 2006. Retargetable Frameworks for Embedded Systems Exploration. IEEE International Conference on Industrial Technology. pp. 2223-2227. 61. Ming, Z. & Jing, L. 2011. The Study on Harmonic Measure Algorithm in Electric Power System Based on DSC. 2011 2nd International Conference on Artificial Intelligence, Management Science and Electronic Commerce (AIMSEC). pp. 6029-6031. 62. Nakano, K. & Ito, Y. 2008. Processor, Assembler, and Compiler Design Education Using an FPGA. 14th IEEE International Conference on Parallel and Distributed System, pp. 723-728. 63. Nery, A. S., Nedjah, N., França, F. M., Jóźwiak, L. & Corporaal, H., 2015. Automatic Complex Instruction Identification For Efficient Application Mapping Onto ApplicationSpecific Instruction Set Processors. Analog Integrated Circuits and Signal Processing, 85, pp. 139-158.164 64. Nery, A. S., Nedjah, N., França, F. M. G., Jozwiak, L. & Corporaal, H. 2014. Automatic Complex Instruction Identification For Efficient Application Mapping Onto ASIPs. IEEE 5th Latin American Symposium on Circuits and Systems. pp. 1-4. 65. Ng, H.-C., Liu, C. & So, H. K.-H., 2016. A Soft Processor Overlay With Tightly-Coupled FPGA Accelerator. 2nd International Workshop on Overlay Architectures for FPGAs, pp. 31-36. 66. Nicola, M., Masera, G., Zamboni, M., Ishebabi, H., Kammler, D., Ascheid, G. & Meyr, H., 2005. FFT Processor: A Case Study in ASIP Development. IST Mobile Summit, pp. 1-5. 67. Pal, A., 2011. Microcontrollers: Principles and Applications, Prentice-Hall of India. 68. Patel, S., 2018. Microgrid Deployment Continues to Grow Worldwide [Online]. Available: http://www.powermag.com/microgrid-deployment-continues-to-grow-worldwide/ [Accessed 2 July 2018]. 69. Patterson, D. A. & Hennessy, J. L., 2013. Computer Organization and Design: The Hardware/Software Interface, Newnes. 70. Peng, F. Z., Li, Y. W. & Tolbert, L. M., 2009. Control and Protection of Power Electronics Interfaced Distributed Generation Systems in A Customer-Driven Microgrid. Power & Energy Society General Meeting, IEEE, pp. 1-8. 71. Peymandoust, A., Pozzi, L., Ienne, P. & Micheli, G. D., 2003. Automatic Instruction Set Extension and Utilization for Embedded Processors. Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 108-118. 72. Plavec, F., 2004. Soft-core Processor Design. Master of Applied Science, University of Toronto.165 73. Plavec, F., Fort, B., Vranesic, Z. G. & Brown, S. D., 2005. Experiences with Soft-Core Processor Design. 19th IEEE International Parallel and Distributed Processing Symposium, pp. 1-4. 74. Pulli, A., Galuzzi, C. & Gaydadjiev, G., 2014. Towards Domain-Specific Instruction-Set Generation. 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1-4. 75. Radhakrishnan, S., Hui, G. & Parameswaran, S., 2004. Dual-Pipeline Heterogeneous ASIP Design. International Conference on Hardware/Software Codesign and System Synthesis, pp. 12-17. 76. Ragel, R. G., Radhakrishnan, S., Ambrose, J. A. & Parameswaran, S., 2013. A Study on Instruction-set Selection Using Multi-Application Based Application Specific InstructionSet Processors. 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems. pp. 7-12. 77. Rajagopal, B. & Singaravelu, S., 2015. Detection of Broken Rotor Bar Fault of Three Phase Induction Motor by Fast Fourier Transform Using ARM Microcontroller. International Journal of Control Theory and Applications, 8, pp. 487-498. 78. Ray, P. K., Puhan, P. S. & Panda, G., 2016. Real Time Harmonics Estimation of Distorted Power System Signal. International Journal of Electrical Power & Energy Systems, 75, pp. 91-98. 79. Reddy, T. D. & Barai, M. 2016. A Novel Configuration to Eliminate Dominant Harmonic frequency (DHF) by Using FFT in Series Active Filters. IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), pp. 1-5. 80. Regazzoni, F. & Ienne, P. 2016. Instruction Set Extensions for Secure Applications. 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, pp. 1529- 1534.166 81. Singh, M. P. & Jain, M. K. 2015. ISA Customization for Application Specific Instruction Set Processors. 2015 International Conference on Pervasive Computing (ICPC). pp. 1-4. 82. Singh, R. P., Vashishtha, A. K. & Krishna, R. 2016. 32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier. 2016 Sixth International Symposium on Embedded Computing and System Design (ISED), IEEE, pp. 112-116. 83. Sinha, S. S., Shah, J. & Nerkar, H., 2016. Harmonics Measurement using FFT Algorithm in Digital Signal Controller for Smart Micro-Grid System. 2016 IEEE Region 10nHumanitarian Technology Conference (R10-HTC), pp. 1-5. 84. Skrien, D., 2001. CPU Sim 3.1: A Tool for Simulating Computer Architectures for Computer Organization Classes. Journal on Educational Resources in Computing (JERIC), 1, pp. 46-59. 85. Smith, S. W., 1997. The Scientist & Engineer's Guide to Digital Signal Processing, California Technical Publishing. 86. Solomon, D., 1993. Assemblers and Loaders, Prentice Hall. 87. Srinivasan, S., Kurella, N., Koren, I. & Kundu, S., 2016. Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors. 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), pp. 563-564. 88. Suppan, H. N., 2008. DLX16: A Compressed 16-bit Instruction Set Architecture (ISA) of DLX Microprocessor. Universiti Teknologi Malaysia. 89. Suto, J., Oniga, S. & Hegyesi, G., 2014. A Simple Fast Fourier Transformation Algorithm to Microcontrollers and Mini Computers. 2014 18th International Conference on Intelligent Engineering Systems (INES), pp. 61-65.167 90. Taglietti, L., Filho, J., Casarotto, D., Furtado, O. & Dos Santos, L., 2005. Automatic ADLBased Assembler Generation for ASIP Programming Support. In: Hämäläinen, T., 91. Pimentel, A., Takala, J. & Vassiliadis, S. (eds.) Embedded Computer Systems: Architectures, Modeling, and Simulation. Springer Berlin / Heidelberg. 92. Tarango, J., Keogh, E. & Brisk, P. 2013. Instruction Set Extensions for Dynamic Time Warping. 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 1-10. 93. Tomar, A. K. S. & Jain, R., 2014. 20-bit RISC and DSP System Design in an FPGA. Computing in Science and Engineering, 16, pp. 16-20. 94. Wang, J., Liang, J., Gao, F., Zhang, L. & Wang, Z., 2015. A Method to Improve the Dynamic Performance of Moving Average Filter-Based PLL. IEEE Trans. Power Electron, 30, pp. 5978-5990. 95. Wang, Y. & Mei, Y. 2015. Electrical measurement system in milling balance machine based on embedded optimization. MIPPR 2015: Remote Sensing Image Processing, Geographic Information Systems, and Other Applications. International Society for Optics and Photonics, pp. 1-7. 96. Wenger, E. & Großschadl, J., 2012. An 8-bit AVR-Based Elliptic Curve Cryptographic RISC Processor for the Internet of Things. 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops. pp. 39-46. 97. Wrona, G., Jasinski, M., Kazmierkowski, M. P., Bobrowska-Rafal, M. & Korzeniewski, M., 2011. Floating point DSP TMS320F28xx in Control Systems for Renewable Energy Sources. Przeglad Elektrotechniczny, 87, pp. 73-78. 98. Xu, X., Clarke, C. T. & Jones, S. R., 2004. High Performance Code Compression Architecture for the Embedded ARM/THUMB Processor. Proceedings of the 1st conference on Computing frontiers. ACM, pp. 451-456.168 99. Yen, W.-F., You, S. D. & Chang, Y.-C., 2009. Real-time FFT with Pre-Calculation. Computers & Electrical Engineering, 35, pp. 435-440. 100. Yiannacouras, P., Steffan, J. G. & Rose, J., 2007. Exploration and Customization of FPGA-Based Soft Processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,, 26, pp. 266-277. 101. Yong, L. E. & Salim, A. J. 2010., Implementation of an 8-bit RISC Microcontroller Chip. 4th International Symposium on Broadband Communication, pp. 1-4. 102. Zhihui, T. & Jianshe, G., 2013. Implementation of the Power Harmonic Measurement Based on FFT and DSP. Journal of Applied Sciences, 13, pp. 1602-1606

Optimized Fast Fourier Transform Architecture Using Instruction Set Architecture Extension In Low-End Digital Signal Controller

Similar Items