14-BIT CMOS hybrid differential DAC for high-resolution sar ADC using VLSI implementation
The advent of highly integrated electronic devices with digitalised architectures have paved the way for the innovation of numerous analogue-to-digital converter (ADC) iterations, such as the successive-approximation-register (SAR) analogue-to-digital converters which benefit from the downscaling in...
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| Format: | Thesis |
| Language: | English English English |
| Published: |
2022
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/10965/4/24p%20MATTHEW%20KHOO%20KAH%20WEN.pdf http://eprints.uthm.edu.my/10965/2/MATTHEW%20KHOO%20KAH%20WEN%20COPYRIGHT%20DECLARATION.pdf http://eprints.uthm.edu.my/10965/3/MATTHEW%20KHOO%20KAH%20WEN%20WATERMARK.pdf |
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| Summary: | The advent of highly integrated electronic devices with digitalised architectures have paved the way for the innovation of numerous analogue-to-digital converter (ADC) iterations, such as the successive-approximation-register (SAR) analogue-to-digital converters which benefit from the downscaling in complementary metal-oxide-semiconductor (CMOS) technology. In this project, emphasis was placed on the design and optimisation of the digital-to-analogue converter (DAC), as it poses an important block of the SAR ADC circuit. Research on previous DAC architectures have exposed several performance limitations in their designs which include low resolution levels, high power consumptions, as well as large differential non-linearity (DNL) errors that come as a result of poor conversion linearity. Therefore, the 14-bit DAC proposed in this project aims to bridge the research gap through the implementation of a differential hybrid design that has the objectives of achieving high resolution, optimum conversion linearity and low power consumption. The proposed circuit is comprised of two separate single-ended DACs that are designed and simulated in the Cadence Virtuoso software using the Silterra 0.18 μm CMOS process with a 2.1V voltage supply. Each of these single-ended blocks utilised a segmented 10-bit resistor DAC (RDAC) and a 4-bit binary-weighted capacitor DAC (CDAC) to formulate the 14-bit hybrid architecture. Switching procedures were also applied to the sub-DAC circuits to ensure a low-power design was established. Detailed transient simulations implemented at the schematic and post-layout levels indicated that the DAC performed the required conversions at a 14-bit precision and maximum conversion frequency of 2.5 MS/s with peak DNL errors of –0.1612 and –0.8272, respectively. The circuit acquired peak power consumption and Signal-to-Noise Ratio (SNR) of 0.1496 mW and 68.94 dB respectively for the standard voltage supply of 2.1 V. Generally, the optimised circuit is capable of carrying out digital-to-analogue conversions at a 14-bit resolution level with low power consumption and DNL errors, thus verifying the high-performance levels of the proposed DAC |
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