New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA

Dynamic symbol size modulation is a type modulation which could provide a fast transmission speed by removing the redundant symbol as compare to fixed symbol size modulation. The dynamic nature of the symbol created an additional problem in hardware design as the size of symbol needed to be defined...

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Main Author: Ilyas, Mohammad Arif
Format: Thesis
Language:English
English
English
Published: 2020
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spelling my-uthm-ep.252021-06-06T08:32:36Z New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA 2020-02 Ilyas, Mohammad Arif TK Electrical engineering. Electronics Nuclear engineering Dynamic symbol size modulation is a type modulation which could provide a fast transmission speed by removing the redundant symbol as compare to fixed symbol size modulation. The dynamic nature of the symbol created an additional problem in hardware design as the size of symbol needed to be defined clearly and it cannot be change and altered once the design has been generated. Thus, to address the issue, this research investigated the best implementation method and performance study of fixed and dynamic symbol size digital baseband modulation for optical communication system in FPGA hardware design. KCU105 FPGA development board and Vivado software were chosen as the main platform to implement the design. A new architecture to implement dynamic symbol size baseband modulation in FPGA is presented in this thesis. Clock control (CC) is used as the research’s based design to create two new architectures which use multiple parallel in serial out (M-PISO) and dynamic parallel in serial out (D-PISO). Next, by using D-PISO architecture, dynamic symbol size modulation namely 8-reverse dual header pulse interval modulation (8-RDHPIM), 8-digital pulse interval modulation (8-DPIM) and fixed symbol size modulation 8-pulse position modulation (8-PPM) were fully implemented in the FPGA which has a transmitter and receiver module. An experimental comparative study was then carried out for each modulation technique. The main parameters investigated were data timing analysis, hardware utilization, power utilization as well as bit error rate performance. From the results, it can be concluded that for power limited system, 8-PPM could be selected as it can maintain a small number of symbol error rate (SER) even during low power transmission which is around -6 dBm. On the other hand, the 8-DPIM and 8-RDHPIM that achieved the transmission speed of 33.3 Mbps and 27.27 Mbps are suitable for systems that require high data speed and minimal clock synchronization. 2020-02 Thesis http://eprints.uthm.edu.my/25/ http://eprints.uthm.edu.my/25/1/24p%20MOHAMMAD%20ARIF%20ILYAS.pdf text en public http://eprints.uthm.edu.my/25/2/MOHAMMAD%20ARIF%20ILYAS%20COPYRIGHT%20DECLARATION.pdf text en staffonly http://eprints.uthm.edu.my/25/3/MOHAMMAD%20ARIF%20ILYAS%20WATERMARK.pdf text en validuser phd doctoral Universiti Tun Hussein Onn Malaysia Fakulti Kejuruteraan Elektrik dan Elektronik
institution Universiti Tun Hussein Onn Malaysia
collection UTHM Institutional Repository
language English
English
English
topic TK Electrical engineering
Electronics Nuclear engineering
spellingShingle TK Electrical engineering
Electronics Nuclear engineering
Ilyas, Mohammad Arif
New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA
description Dynamic symbol size modulation is a type modulation which could provide a fast transmission speed by removing the redundant symbol as compare to fixed symbol size modulation. The dynamic nature of the symbol created an additional problem in hardware design as the size of symbol needed to be defined clearly and it cannot be change and altered once the design has been generated. Thus, to address the issue, this research investigated the best implementation method and performance study of fixed and dynamic symbol size digital baseband modulation for optical communication system in FPGA hardware design. KCU105 FPGA development board and Vivado software were chosen as the main platform to implement the design. A new architecture to implement dynamic symbol size baseband modulation in FPGA is presented in this thesis. Clock control (CC) is used as the research’s based design to create two new architectures which use multiple parallel in serial out (M-PISO) and dynamic parallel in serial out (D-PISO). Next, by using D-PISO architecture, dynamic symbol size modulation namely 8-reverse dual header pulse interval modulation (8-RDHPIM), 8-digital pulse interval modulation (8-DPIM) and fixed symbol size modulation 8-pulse position modulation (8-PPM) were fully implemented in the FPGA which has a transmitter and receiver module. An experimental comparative study was then carried out for each modulation technique. The main parameters investigated were data timing analysis, hardware utilization, power utilization as well as bit error rate performance. From the results, it can be concluded that for power limited system, 8-PPM could be selected as it can maintain a small number of symbol error rate (SER) even during low power transmission which is around -6 dBm. On the other hand, the 8-DPIM and 8-RDHPIM that achieved the transmission speed of 33.3 Mbps and 27.27 Mbps are suitable for systems that require high data speed and minimal clock synchronization.
format Thesis
qualification_name Doctor of Philosophy (PhD.)
qualification_level Doctorate
author Ilyas, Mohammad Arif
author_facet Ilyas, Mohammad Arif
author_sort Ilyas, Mohammad Arif
title New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA
title_short New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA
title_full New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA
title_fullStr New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA
title_full_unstemmed New d-piso architecture for dynamic symbol size digital baseband modulation implementation in FPGA
title_sort new d-piso architecture for dynamic symbol size digital baseband modulation implementation in fpga
granting_institution Universiti Tun Hussein Onn Malaysia
granting_department Fakulti Kejuruteraan Elektrik dan Elektronik
publishDate 2020
url http://eprints.uthm.edu.my/25/1/24p%20MOHAMMAD%20ARIF%20ILYAS.pdf
http://eprints.uthm.edu.my/25/2/MOHAMMAD%20ARIF%20ILYAS%20COPYRIGHT%20DECLARATION.pdf
http://eprints.uthm.edu.my/25/3/MOHAMMAD%20ARIF%20ILYAS%20WATERMARK.pdf
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