Design of low power high speed digital vedic multiplier using 13T hybrid full adder

The increment of demand for battery operated portable devices has laid emphasis on the development of low power multiplier and high performance systems. Multiplier is omnipresent in most common circuits; and adders act as the main block for the multiplier to operate. Performance of full adder had di...

Full description

Saved in:
Bibliographic Details
Main Author: Lee, Shing Jie
Format: Thesis
Language:English
English
English
Published: 2018
Subjects:
Online Access:http://eprints.uthm.edu.my/428/1/24p%20LEE%20SHING%20JEE.pdf
http://eprints.uthm.edu.my/428/2/LEE%20SHING%20JIE%20COPYRIGHT%20DECLARATION.pdf
http://eprints.uthm.edu.my/428/3/LEE%20SHING%20JIE%20WATERMARK.pdf
Tags: Add Tag
No Tags, Be the first to tag this record!
id my-uthm-ep.428
record_format uketd_dc
spelling my-uthm-ep.4282021-07-25T03:08:34Z Design of low power high speed digital vedic multiplier using 13T hybrid full adder 2018-06 Lee, Shing Jie QA76 Computer software The increment of demand for battery operated portable devices has laid emphasis on the development of low power multiplier and high performance systems. Multiplier is omnipresent in most common circuits; and adders act as the main block for the multiplier to operate. Performance of full adder had direct impact in all arithmetic circuits. In this thesis, a 4x4 bit Vedic multiplier has been successfully designed using the combination of Urdhva Triyakbyam Sutras and 13 transistors (13T) hybrid full adder (HFA). The Urdhva Triyakbyam algorithm satisfies the requirement of a fast multiplication operation which reduced large number of partial products when compared to others. Meanwhile the HFA is a new designed adder which is proposed in this thesis is able to produce full output voltage swing output using low power consumption (18.97 μW) and least delay (46.8 ps). The multiplier is designed and simulated at the transistor level circuit and the layout circuit using Synopsys EDA Tools with Process Design Kit (PDK) of 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology. With a 1 V voltage supply associated with load capacitance of 0.1 pF, this 4x4 bit Vedic multiplier is able to produce an output with the power consumption of 0.2015 mW, delay of 376 ps and a compact area which only consumed 3100 μm2 (54.39 μm x 57.00 μm). The number of transistor for this multiplier is only 356 transistors. Novelty SUM circuit that newly designed in this project had a huge contribution in reducing the transistors count from 6T to 4T. With the reduction of transistors count in this circuit, the overall power consumption, the delay time and the layout had been reduced. 2018-06 Thesis http://eprints.uthm.edu.my/428/ http://eprints.uthm.edu.my/428/1/24p%20LEE%20SHING%20JEE.pdf text en public http://eprints.uthm.edu.my/428/2/LEE%20SHING%20JIE%20COPYRIGHT%20DECLARATION.pdf text en staffonly http://eprints.uthm.edu.my/428/3/LEE%20SHING%20JIE%20WATERMARK.pdf text en validuser mphil masters Universiti Tun Hussein Onn Malaysia Faculty of Electrical and Electronic Engineering
institution Universiti Tun Hussein Onn Malaysia
collection UTHM Institutional Repository
language English
English
English
topic QA76 Computer software
spellingShingle QA76 Computer software
Lee, Shing Jie
Design of low power high speed digital vedic multiplier using 13T hybrid full adder
description The increment of demand for battery operated portable devices has laid emphasis on the development of low power multiplier and high performance systems. Multiplier is omnipresent in most common circuits; and adders act as the main block for the multiplier to operate. Performance of full adder had direct impact in all arithmetic circuits. In this thesis, a 4x4 bit Vedic multiplier has been successfully designed using the combination of Urdhva Triyakbyam Sutras and 13 transistors (13T) hybrid full adder (HFA). The Urdhva Triyakbyam algorithm satisfies the requirement of a fast multiplication operation which reduced large number of partial products when compared to others. Meanwhile the HFA is a new designed adder which is proposed in this thesis is able to produce full output voltage swing output using low power consumption (18.97 μW) and least delay (46.8 ps). The multiplier is designed and simulated at the transistor level circuit and the layout circuit using Synopsys EDA Tools with Process Design Kit (PDK) of 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology. With a 1 V voltage supply associated with load capacitance of 0.1 pF, this 4x4 bit Vedic multiplier is able to produce an output with the power consumption of 0.2015 mW, delay of 376 ps and a compact area which only consumed 3100 μm2 (54.39 μm x 57.00 μm). The number of transistor for this multiplier is only 356 transistors. Novelty SUM circuit that newly designed in this project had a huge contribution in reducing the transistors count from 6T to 4T. With the reduction of transistors count in this circuit, the overall power consumption, the delay time and the layout had been reduced.
format Thesis
qualification_name Master of Philosophy (M.Phil.)
qualification_level Master's degree
author Lee, Shing Jie
author_facet Lee, Shing Jie
author_sort Lee, Shing Jie
title Design of low power high speed digital vedic multiplier using 13T hybrid full adder
title_short Design of low power high speed digital vedic multiplier using 13T hybrid full adder
title_full Design of low power high speed digital vedic multiplier using 13T hybrid full adder
title_fullStr Design of low power high speed digital vedic multiplier using 13T hybrid full adder
title_full_unstemmed Design of low power high speed digital vedic multiplier using 13T hybrid full adder
title_sort design of low power high speed digital vedic multiplier using 13t hybrid full adder
granting_institution Universiti Tun Hussein Onn Malaysia
granting_department Faculty of Electrical and Electronic Engineering
publishDate 2018
url http://eprints.uthm.edu.my/428/1/24p%20LEE%20SHING%20JEE.pdf
http://eprints.uthm.edu.my/428/2/LEE%20SHING%20JIE%20COPYRIGHT%20DECLARATION.pdf
http://eprints.uthm.edu.my/428/3/LEE%20SHING%20JIE%20WATERMARK.pdf
_version_ 1747830607685091328