Simulation studies of 30 MHz phase-locked loop coherent receiver
Phase-Locked Loop or in short PLL is a vital part in electronics system mainly in communication system in getting back the transmitted signal. As a whole, it is basically a closed loop frequency control system where its function is based on the phase sensitive detection of phase difference bet...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English English English |
| Published: |
2005
|
| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/7645/1/24p%20FAUZI%20ABDUL%20WAHAB.pdf http://eprints.uthm.edu.my/7645/2/FAUZI%20ABDUL%20WAHAB%20COPYRIGHT%20DECLARATION.pdf http://eprints.uthm.edu.my/7645/3/FAUZI%20ABDUL%20WAHAB%20WATERMARK.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Phase-Locked Loop or in short PLL is a vital part in electronics system
mainly in communication system in getting back the transmitted signal. As a whole,
it is basically a closed loop frequency control system where its function is based on
the phase sensitive detection of phase difference between the input signal
(transmitted signal) and the output of the controlled oscillation. Although the system
had been around since 1930's, implemented by the French Engineer, H. De
Bellescise, but still, until today further development is in progress in achieving better
response and performance in retrieving and synchronising transmitted signals. The
purpose of this project is to familiarise in designing and constructing a 30 MHz
Phase-Locked Loop Coherent Receiver by computer simulation, taking account the
requirements for each building block of a PLL system, the stability of the system and
the response of the system. To achieve this, the process includes simple and direct
calculations, and circuit simulations observation. Results are represented in graphs
and are analysed. |
|---|