Implementation of luo-rudi phase 1 cardiac cell excitation model in FPGA
Dynamic simulation of complex cardiac excitation and conduction requires high computational time. Thus, the hardware techniques that can run in the real-time simulation was introduced. However, previously developed hardware simulation requires high power consumption and has a large physical size. Du...
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| Format: | Thesis |
| Language: | English English English |
| Published: |
2017
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/7827/1/24p%20NORLIZA%20OTHMAN.pdf http://eprints.uthm.edu.my/7827/2/NORLIZA%20OTHMAN%20COPYRIGHT%20DECLARATION.pdf http://eprints.uthm.edu.my/7827/3/NORLIZA%20OTHMAN%20WATERMARK.pdf |
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| Summary: | Dynamic simulation of complex cardiac excitation and conduction requires high computational time. Thus, the hardware techniques that can run in the real-time simulation was introduced. However, previously developed hardware simulation requires high power consumption and has a large physical size. Due to the drawbacks, this research presents the adaptation of Luo-Rudy Phase I (LR-I) cardiac excitation model in a rapid prototyping method of field programmable gate array (FPGA) for real-time simulation, lower power consumption and minimizing the size. For the rapid prototyping, a nonlinear Ordinary Differential Equation (ODE)based algorithm of the LR-I model is implemented by using Hardware Description Language (I-IDL) Coder that is capable to convert MATLAB Simulink blocks designed into a synthesisable VHSIC Hardware Description Language (VHDL) code and verified using the FPGA-In-the Loop (FIL) Co-simulator. The Xilinx FPGA Yirtex-6 XC6VLX240T ML605 evaluation board is chosen as a platform for the FPGA high performance system which is supported by the 1-lDL Coder. A fixedpoint optimisation has been successfully obtained with Percentage Error (PE) and Mean Square Error (MSE) which are -1.08% and 2.28%, respectively. This result has given better performance for the hardware implementation in terms of 27.5% decrement in power consumption and 5.35% decrement in utilization area with maximum frequency 9.819 MHz. By implementing the constructed algorithm into the high performance FPGA system, a new real-time simulation-based analysis technique of cardiac electrical excitation has been successfully developed. |
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