Variable oxide thickness optimization and reliability analysis of Gate-All-Around floating gate for flash memory cell
Gate-All-Around (GAA) transistor is one of the excellent devices that has been utilized for flash memory applications owing to its gate coupling which led to a higher gate electrostatic control, cheaper manufacturing cost and bigger data storage. However, GAA structure with floating gate memory cell...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2020
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/102451/1/FarahAHamidMSKE2020.pdf |
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| Summary: | Gate-All-Around (GAA) transistor is one of the excellent devices that has been utilized for flash memory applications owing to its gate coupling which led to a higher gate electrostatic control, cheaper manufacturing cost and bigger data storage. However, GAA structure with floating gate memory cell may suffer from cell-to-cell interference resulting in higher operational voltage. One of the effective solutions for lowering the program/erase (P/E) voltage is by down-scaling the tunnel oxide thickness. However, scaling down the tunnel dielectric layer may degrade the data retention and endurance due to stress induced leakage current (SILC). Thus, a concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack has been implemented on Gate-All-Around Floating Gate (GAA-FG) memory cell to reduce P/E operational voltage, to improve the efficiency of data retention after 10years and endurance after 104 of P/E cycles. This research begins with the VARIOT optimization of five high-k dielectric materials which are Zirconium dioxide, Hafnium (IV) Oxide, Lanthanum Oxide, Yttrium (III) Oxide, and Aluminium Oxide (ZrO2, HfO2, La2O3, Y2O3 and Al2O3) in which these high-k dielectrics can be embedded onto low-k dielectric layer which is Silicon Dioxide, SiO2 using 3-Dimensional (3D) TCAD simulator of Silvaco ATLAS. Then, the transient performances of the GAA-FG memory cell with optimized parameters are assessed to offset the trade-off between P/E characteristics and the device reliability including data retention and endurance. From VARIOT optimization, interestingly, it is found that SiO2/La2O3 asymmetric stack has become a promising candidate to improve the P/E characteristics and the reliability of GAA-FG memory cell due to the lowest programming voltage compared to other high-k dielectric materials. By using P/E operational voltage of 10/-12V, 20% improvement of threshold window has been observed for SiO2/La2O3 stack compared to conventional single tunnel layer of SiO2. Based on the proposed approach, the data retention slightly degrades by only ~5% after 10 years of extrapolation and reasonable P/E endurance is obtained with only ~16% loss after 104 of P/E cycles. Apparently, these findings indicate that better performances of GAA-FG memory cell with the incorporation of SiO2/La2O3 tunnel layer which can be used to assist experimental work. |
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