Verilog modelling of Modbus TCP at 100 mbps

Verilog modelling of Modbus TCP at 100 mbps

With the continuous development of industry automation, industrial control systems and programmable logic devices are being widely used in the manufacturing production. Machines are required to work either in connection to each other or remotely controlled at a centralized control room using Interne...

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Main Author: Tan, Zhe Jie
Format: Thesis
Language:English
Published: 2022
Subjects:
TK Electrical engineering
Electronics Nuclear engineering
Online Access:http://eprints.utm.my/102726/1/TanZheJieMSKE2022.pdf.pdf
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spelling my-utm-ep.1027262023-09-20T03:25:05Z Verilog modelling of Modbus TCP at 100 mbps 2022 Tan, Zhe Jie TK Electrical engineering. Electronics Nuclear engineering With the continuous development of industry automation, industrial control systems and programmable logic devices are being widely used in the manufacturing production. Machines are required to work either in connection to each other or remotely controlled at a centralized control room using Internet of Things (IoT), Supervisory Control and Data Acquisition Systems (SCADA) or other communication means. Among the many industrial networking protocols, Modbus TCP is widely adopted. Software implementation of Modbus TCP network is common in the industry. Although software does the job, it is a burden to the processor. There are also Modbus TCP hardware modules selling in the market. But dedicated hardware incurs high cost and not scalable for any feature change. Hence, this project aims to analyse and design a hardware Modbus TCP client and server communication node with the help of RTL-ASMChart and Petri Net. It will be implemented at 100Mbps Ethernet speed within the appropriate power, performance, and area. This design is coded in SystemVerilog and validation is done in Quartus ModelSim simulation. Running testbench in ModelSim and Wireshark show the design is function as expected, after it can be compiled and fit into the target Cyclone V FPGA. Timing closure and throughput expectation of 100Mbps is met in Quartus, with power consumption of around 350mW. Round trip test results showed that RTL designed TCP module has speed improvement over the software TCP method of Windows operating system. 2022 Thesis http://eprints.utm.my/102726/ http://eprints.utm.my/102726/1/TanZheJieMSKE2022.pdf.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149740 masters Universiti Teknologi Malaysia Faculty of Engineering - School of Electrical Engineering
institution Universiti Teknologi Malaysia
collection UTM Institutional Repository
language English
topic TK Electrical engineering
Electronics Nuclear engineering
spellingShingle TK Electrical engineering
Electronics Nuclear engineering
Tan, Zhe Jie
Verilog modelling of Modbus TCP at 100 mbps
description With the continuous development of industry automation, industrial control systems and programmable logic devices are being widely used in the manufacturing production. Machines are required to work either in connection to each other or remotely controlled at a centralized control room using Internet of Things (IoT), Supervisory Control and Data Acquisition Systems (SCADA) or other communication means. Among the many industrial networking protocols, Modbus TCP is widely adopted. Software implementation of Modbus TCP network is common in the industry. Although software does the job, it is a burden to the processor. There are also Modbus TCP hardware modules selling in the market. But dedicated hardware incurs high cost and not scalable for any feature change. Hence, this project aims to analyse and design a hardware Modbus TCP client and server communication node with the help of RTL-ASMChart and Petri Net. It will be implemented at 100Mbps Ethernet speed within the appropriate power, performance, and area. This design is coded in SystemVerilog and validation is done in Quartus ModelSim simulation. Running testbench in ModelSim and Wireshark show the design is function as expected, after it can be compiled and fit into the target Cyclone V FPGA. Timing closure and throughput expectation of 100Mbps is met in Quartus, with power consumption of around 350mW. Round trip test results showed that RTL designed TCP module has speed improvement over the software TCP method of Windows operating system.
format Thesis
qualification_level Master's degree
author Tan, Zhe Jie
author_facet Tan, Zhe Jie
author_sort Tan, Zhe Jie
title Verilog modelling of Modbus TCP at 100 mbps
title_short Verilog modelling of Modbus TCP at 100 mbps
title_full Verilog modelling of Modbus TCP at 100 mbps
title_fullStr Verilog modelling of Modbus TCP at 100 mbps
title_full_unstemmed Verilog modelling of Modbus TCP at 100 mbps
title_sort verilog modelling of modbus tcp at 100 mbps
granting_institution Universiti Teknologi Malaysia
granting_department Faculty of Engineering - School of Electrical Engineering
publishDate 2022
url http://eprints.utm.my/102726/1/TanZheJieMSKE2022.pdf.pdf
_version_ 1783729213054910464

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