VHDL implementation of pipelined DLX microprocessor

The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good archit...

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Main Author:	Anthony, Ignatius Edmond
Format:	Thesis
Language:	English
Published:	2008
Subjects:	QA75 Electronic computers Computer science
Online Access:	http://eprints.utm.my/id/eprint/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf
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id	my-utm-ep.11462
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spelling	my-utm-ep.114622018-07-23T05:37:13Z VHDL implementation of pipelined DLX microprocessor 2008-05 Anthony, Ignatius Edmond QA75 Electronic computers. Computer science TK Electrical engineering. Electronics Nuclear engineering The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good architectural model for study, not only because of the popularity of this type of machine, but also because it is easy to understand. Utilizing open source hardware such as the DLX core yields the apparent advantage of free-for-all distribution as well as having source codes that are is available and open, allowing for source code modification at-will. This project aims to continue previous work on integration of the DLX core by adding instruction pipelining which was excluded from the previous project’s scope due to complexity and time limitations. Instruction execution speedup and performance was left on the table to be dealt with in future work. Since the DLX microprocessor was, by nature, a 5-stage pipelined microprocessor, it can be expected that the core’s performance on instruction execution can be sped up with a pipeline implementation. Comparison between the non-pipelined and pipelined DLX were also performed to verify this instruction execution speedup expectation. 2008-05 Thesis http://eprints.utm.my/id/eprint/11462/ http://eprints.utm.my/id/eprint/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering 1. Hennessy, John L and Peterson, David A (1990). Computer Architecture: A Quantitative Approach. USA: Morgan Kauffmann. San Francisco, USA. 2. Rajagopal, Selvakumar. FPGA Implementation of DLX Microprocessor with Wishbone SoC Bus. Bachelor’s Thesis. Universiti Teknologi Malaysia; 2005 3. Amde, M.; Blunno, I. and Sotiriou, C.P.; (2003). Automating the Design of an Asynchronous DLX Microprocessor. Proceedings of 40th Design Automation Conference (DAC), 2-6 June 2003 Page(s):502 - 507. 4. Gumm, Martin (1995). VHDL Modeling and Synthesis of the DLXS RISC Processor. Germany: University of Stuttgart 5. Buhler, M. and Baitinger, U.G.(1998). VHDL-based development of a 32-bit pipelined RISC processor for educational purposes, Ninth Mediterranean Electrotechnical Conference (MELECON 98), Volume 1, 18-20 May 1998 Page(s):138 - 142 vol.1. 6. Ashenden, Peter J. (2002). The Designer’s Guide to VHDL, 2e, Morgan Kaufmann, San Francisco.
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	QA75 Electronic computers Computer science QA75 Electronic computers Computer science
spellingShingle	QA75 Electronic computers Computer science QA75 Electronic computers Computer science Anthony, Ignatius Edmond VHDL implementation of pipelined DLX microprocessor
description	The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good architectural model for study, not only because of the popularity of this type of machine, but also because it is easy to understand. Utilizing open source hardware such as the DLX core yields the apparent advantage of free-for-all distribution as well as having source codes that are is available and open, allowing for source code modification at-will. This project aims to continue previous work on integration of the DLX core by adding instruction pipelining which was excluded from the previous project’s scope due to complexity and time limitations. Instruction execution speedup and performance was left on the table to be dealt with in future work. Since the DLX microprocessor was, by nature, a 5-stage pipelined microprocessor, it can be expected that the core’s performance on instruction execution can be sped up with a pipeline implementation. Comparison between the non-pipelined and pipelined DLX were also performed to verify this instruction execution speedup expectation.
format	Thesis
qualification_level	Master's degree
author	Anthony, Ignatius Edmond
author_facet	Anthony, Ignatius Edmond
author_sort	Anthony, Ignatius Edmond
title	VHDL implementation of pipelined DLX microprocessor
title_short	VHDL implementation of pipelined DLX microprocessor
title_full	VHDL implementation of pipelined DLX microprocessor
title_fullStr	VHDL implementation of pipelined DLX microprocessor
title_full_unstemmed	VHDL implementation of pipelined DLX microprocessor
title_sort	vhdl implementation of pipelined dlx microprocessor
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2008
url	http://eprints.utm.my/id/eprint/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf
_version_	1747814858392338432

VHDL implementation of pipelined DLX microprocessor

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