VHDL implementation of pipelined DLX microprocessor
The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good archit...
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| 主要作者: | |
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| 格式: | Thesis |
| 语言: | English |
| 出版: |
2008
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| 主题: | |
| 在线阅读: | http://eprints.utm.my/id/eprint/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf |
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