VHDL implementation of pipelined DLX microprocessor
The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good archit...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English |
| 出版: |
2008
|
| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
成為第一個發表評論!