Scalable multicore design for test interface design
With industries moving towards converged core design, and multicore processors products, DFx design and testing strategy need to be able to catch up with the pace of product development cycle, increase in test content and test time, as well as converged core design reuse in proliferation of products...
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my-utm-ep.115772018-07-30T08:39:35Z Scalable multicore design for test interface design 2007-11 Chong, Shi Hou QA75 Electronic computers. Computer science TK Electrical engineering. Electronics Nuclear engineering With industries moving towards converged core design, and multicore processors products, DFx design and testing strategy need to be able to catch up with the pace of product development cycle, increase in test content and test time, as well as converged core design reuse in proliferation of products. As such, core-level test content must be reusable, multicore testing have to be done concurrently, while allow the choice of core isolation, as well as DFx multicore interface that are scalable to facilitate proliferation of products. The main objectives of this project are to investigate on major problems of multicore Design For Testability interface design, to analyze and understand pros and cons of multiple industrial multicore Design For Testability interface designs, to propose and to implement a novel design that can tackle three major problems in term of multicore Design For Testability interface design scalability, concurrent testability as well as trace reusability. 2007-11 Thesis http://eprints.utm.my/id/eprint/11577/ http://eprints.utm.my/id/eprint/11577/1/ChongShiHouMFKE2008.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering 1. Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, and Rohit Kapur. “Overview of the IEEE P1500 Standard”. 2003 International Test Conference, pp. 988-997. 2. IEEE P1500 Web Site. http://grouper.ieee.org/groups/1500/. 3. Lee Whetsel. “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores”. 1997 International Test Conference, pp. 69-78. 4. Steve Oakland. “Considerations for Implementing IEEE 1149.1 on System-on-a- Chip Integrated Circuits”. 2000 International Test Conference, pp. 628-637. 5. Ishwar Parulkar, Thomas Ziaja, Rajesh Pendurkar, Anand D’Souza, and Amitava Majumdar. “A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC Chip Multi-Processors”. 2002 International Test Conference, pp. 726-735 6. Yuejian Wu and Paul MacDonald, Member, IEEE. “Testing ASICs with Multiple Identical Cores”. 2003 IEEE Trans. Comput., pp327-336 7. Bart Vermeulen, Tom Waayers, and Sjaak Bakker. “IEEE 1149.1-compliant Access Architecure for Multiple Core Debug on Digiral System Chips”. 2002 International Test Conference, pp.55-63 8. Adam Osseiram. “Test Standards (With Focus on IEEE1149.1)”. 1996 IEEE , pp.708-711 9. “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Computer Society, February 1990. |
| institution |
Universiti Teknologi Malaysia |
| collection |
UTM Institutional Repository |
| language |
English |
| topic |
QA75 Electronic computers Computer science QA75 Electronic computers Computer science |
| spellingShingle |
QA75 Electronic computers Computer science QA75 Electronic computers Computer science Chong, Shi Hou Scalable multicore design for test interface design |
| description |
With industries moving towards converged core design, and multicore processors products, DFx design and testing strategy need to be able to catch up with the pace of product development cycle, increase in test content and test time, as well as converged core design reuse in proliferation of products. As such, core-level test content must be reusable, multicore testing have to be done concurrently, while allow the choice of core isolation, as well as DFx multicore interface that are scalable to facilitate proliferation of products. The main objectives of this project are to investigate on major problems of multicore Design For Testability interface design, to analyze and understand pros and cons of multiple industrial multicore Design For Testability interface designs, to propose and to implement a novel design that can tackle three major problems in term of multicore Design For Testability interface design scalability, concurrent testability as well as trace reusability. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Chong, Shi Hou |
| author_facet |
Chong, Shi Hou |
| author_sort |
Chong, Shi Hou |
| title |
Scalable multicore design for test interface design |
| title_short |
Scalable multicore design for test interface design |
| title_full |
Scalable multicore design for test interface design |
| title_fullStr |
Scalable multicore design for test interface design |
| title_full_unstemmed |
Scalable multicore design for test interface design |
| title_sort |
scalable multicore design for test interface design |
| granting_institution |
Universiti Teknologi Malaysia, Faculty of Electrical Engineering |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2007 |
| url |
http://eprints.utm.my/id/eprint/11577/1/ChongShiHouMFKE2008.pdf |
| _version_ |
1747814872382439424 |