Development of single board computer based on 32-bit 5-stage pipeline RISC processor
In 21st century, embedded system design is a popular alternative to typical microprocessor design as it takes advantage of application characteristics to optimize its design for adequate performance at lower cost. Single Board Computer is a standalone digital system which capable to perform logical...
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| Format: | Thesis |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/12351/6/KoayBoonWooiMFKE2009.pdf |
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| Summary: | In 21st century, embedded system design is a popular alternative to typical microprocessor design as it takes advantage of application characteristics to optimize its design for adequate performance at lower cost. Single Board Computer is a standalone digital system which capable to perform logical computation and data manipulation. Single Board Computer has CPU (Central Processing Unit), memory controller hub and I/O devices controller hub (interface chip) embedded to a single platform such as SoC (System-on-Chip) and embedded system. It is an economical and portable digital system with optimum logic gates and devices utilization. Single Board Computer has capability to synchronize data transfer between CPU and I/O peripheral devices, perform CPU operation as well as running program coded in machine code that utilize all its interfacing hardware devices. This thesis proposes a design of Single Board Computer in Verilog RTL, by extending from previous UTM student’s research on 32-bit 5-stage pipeline RISC processor, targeted at FPGA implementation in System-on-Chip (SoC) designs. ISA (Instruction Set Architecture) of RISC(Reduced Instructions Set Computer) processor is enhanced to cover control instruction. I/O controllers are designed to support insertion of input data and display of output data. This Single Board Computer is designed in compact form and generalized to comply with RISC CPU specifications and some basic I/O protocols, which will be a valuable asset in UTM soft core IP bank as to help in its future SoC researches. |
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