Development of single board computer based on 32-bit 5-stage pipeline RISC processor

Development of single board computer based on 32-bit 5-stage pipeline RISC processor

In 21st century, embedded system design is a popular alternative to typical microprocessor design as it takes advantage of application characteristics to optimize its design for adequate performance at lower cost. Single Board Computer is a standalone digital system which capable to perform logical...

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Main Author: Koay, Boon Wooi
Format: Thesis
Language:English
Published: 2009
Subjects:
QA75 Electronic computers
Computer science
Online Access:http://eprints.utm.my/id/eprint/12351/6/KoayBoonWooiMFKE2009.pdf
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spelling my-utm-ep.123512017-09-17T05:47:22Z Development of single board computer based on 32-bit 5-stage pipeline RISC processor 2009-11 Koay, Boon Wooi QA75 Electronic computers. Computer science In 21st century, embedded system design is a popular alternative to typical microprocessor design as it takes advantage of application characteristics to optimize its design for adequate performance at lower cost. Single Board Computer is a standalone digital system which capable to perform logical computation and data manipulation. Single Board Computer has CPU (Central Processing Unit), memory controller hub and I/O devices controller hub (interface chip) embedded to a single platform such as SoC (System-on-Chip) and embedded system. It is an economical and portable digital system with optimum logic gates and devices utilization. Single Board Computer has capability to synchronize data transfer between CPU and I/O peripheral devices, perform CPU operation as well as running program coded in machine code that utilize all its interfacing hardware devices. This thesis proposes a design of Single Board Computer in Verilog RTL, by extending from previous UTM student’s research on 32-bit 5-stage pipeline RISC processor, targeted at FPGA implementation in System-on-Chip (SoC) designs. ISA (Instruction Set Architecture) of RISC(Reduced Instructions Set Computer) processor is enhanced to cover control instruction. I/O controllers are designed to support insertion of input data and display of output data. This Single Board Computer is designed in compact form and generalized to comply with RISC CPU specifications and some basic I/O protocols, which will be a valuable asset in UTM soft core IP bank as to help in its future SoC researches. 2009-11 Thesis http://eprints.utm.my/id/eprint/12351/ http://eprints.utm.my/id/eprint/12351/6/KoayBoonWooiMFKE2009.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering 1. Lim Jonie, The RTL Design of 32-Bit 5-Stage Pipeline RISC Processor using Verilog HDL, UTM. 2008 2. Wikipedia, Classic RISC pipeline, wikipedia.org., 2009 http://en.wikipedia.org/wiki/Classic_RISC_pipeline 3. Wikipedia, Single-board computer, wikipedia.org., 2009 http://en.wikipedia.org/wiki/Single-board_computer 4. Jurij Silc, Advanced Processor Architecture, http://csd.ijs.si/silc 5. Wikipedia, Booting,wikipedia.org, 2009 http://en.wikipedia.org/wiki/Booting 6. Avinash Rajah, VLSI Design of Neurohardware Processor Implementing The Kohonen Neural Network Algorithm, UTM, 2005 7. 101 Innovation Drive, Avalon Interface Specification, Altera, Oct. 2008 8. Adam Chapweske, The PS/2 Mouse/Keyboard Protocol, Computer- Engineering.org, http://www.Computer-Engineering.org/ps2protocol 9. Craig Peacock, Interfacing the PC’s Keyboard, beyondlogic.org.2005, http://www.beyondlogic.org/keyboard/keybrd.htm 10. Peter Ouwehand, How to control a HD44780-based Character-LCD, 2005 http://home.iae.nl/users/pouweha/lcd/lcd0.shtml 11. Dr. Mohamed Khalil Hani, Starter’s Guide to Digital Systems VHDL & Verilog Design, UTM. 2008. 12. V.P. Heuring & H.F. Jordan, Computer Systems Design & Architecture, Pearson Prentice-Hall, 2004 13. Stephen Brown & Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, McGraw-Hill, 2004 14. J.O.Hamblen & T.S.Hall., Using System-on-a-Programmable-Chip Technology to Design Embedded Systems, ISCA Vol.13, No.3, Sept. 2006 15. Wael M El-Medany & Khalid A Al-Khooheji, Design and Implementation of a 32bit RISC Processor on Xilinx FPGA, University Of Bahrain, 2006
institution Universiti Teknologi Malaysia
collection UTM Institutional Repository
language English
topic QA75 Electronic computers
Computer science
spellingShingle QA75 Electronic computers
Computer science
Koay, Boon Wooi
Development of single board computer based on 32-bit 5-stage pipeline RISC processor
description In 21st century, embedded system design is a popular alternative to typical microprocessor design as it takes advantage of application characteristics to optimize its design for adequate performance at lower cost. Single Board Computer is a standalone digital system which capable to perform logical computation and data manipulation. Single Board Computer has CPU (Central Processing Unit), memory controller hub and I/O devices controller hub (interface chip) embedded to a single platform such as SoC (System-on-Chip) and embedded system. It is an economical and portable digital system with optimum logic gates and devices utilization. Single Board Computer has capability to synchronize data transfer between CPU and I/O peripheral devices, perform CPU operation as well as running program coded in machine code that utilize all its interfacing hardware devices. This thesis proposes a design of Single Board Computer in Verilog RTL, by extending from previous UTM student’s research on 32-bit 5-stage pipeline RISC processor, targeted at FPGA implementation in System-on-Chip (SoC) designs. ISA (Instruction Set Architecture) of RISC(Reduced Instructions Set Computer) processor is enhanced to cover control instruction. I/O controllers are designed to support insertion of input data and display of output data. This Single Board Computer is designed in compact form and generalized to comply with RISC CPU specifications and some basic I/O protocols, which will be a valuable asset in UTM soft core IP bank as to help in its future SoC researches.
format Thesis
qualification_level Master's degree
author Koay, Boon Wooi
author_facet Koay, Boon Wooi
author_sort Koay, Boon Wooi
title Development of single board computer based on 32-bit 5-stage pipeline RISC processor
title_short Development of single board computer based on 32-bit 5-stage pipeline RISC processor
title_full Development of single board computer based on 32-bit 5-stage pipeline RISC processor
title_fullStr Development of single board computer based on 32-bit 5-stage pipeline RISC processor
title_full_unstemmed Development of single board computer based on 32-bit 5-stage pipeline RISC processor
title_sort development of single board computer based on 32-bit 5-stage pipeline risc processor
granting_institution Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department Faculty of Electrical Engineering
publishDate 2009
url http://eprints.utm.my/id/eprint/12351/6/KoayBoonWooiMFKE2009.pdf
_version_ 1747814926818213888

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