Implementation of reconfigurable viterbi decoders in hardware

Channel coders are widely used in digital transmissions where data can be corrupted due to interference. They are used in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital television broadcast, compact disc, and magnetic disk rea...

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Main Author:	Noor Batcha, Mohamed Farid
Format:	Thesis
Language:	English
Published:	2010
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/12722/1/MohamedFaridNoorMFKE2010.pdf
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spelling	my-utm-ep.127222017-09-13T04:28:40Z Implementation of reconfigurable viterbi decoders in hardware 2010 Noor Batcha, Mohamed Farid TK Electrical engineering. Electronics Nuclear engineering Channel coders are widely used in digital transmissions where data can be corrupted due to interference. They are used in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital television broadcast, compact disc, and magnetic disk reading. Viterbi decoder is one of the most widely used channel decoders that are used for decoding data that are encoded using convolutional forward error correction codes. This research investigates an adaptive channel coder that is able to switch between few configurations depending on the channel conditions. Channel codes consist of encoders and decoders, and since encoders are rather simple, the main focus of the research is towards the decoders. The research explores into an optimized shared hardware structure between various Viterbi decoders especially of those being used in current technologies such as General Packet Radio Service (GPRS), Enhanced Data rates for GSM Evolution (EDGE), and Worldwide Interoperability for Microwave Access (Wimax). The research looks into optimized methods of memory management and is also aimed for high throughput to be used for high speed applications that are a trend for new and upcoming technologies. Initially the performance of various configuration of Viterbi decoder with respect to different channel conditions was looked into to select few suitable Viterbi decoders to be implemented on Field Programmable Gate Array (FPGA). The final implementation on FPGA combines three Viterbi decoders into a single core. The gain in area of the three Viterbi existing separately when compared to the joint hardware is about 15 %, with no loss in processing speed and throughput. The latency is measured to be a minimum amount with respect to the data size. For a packet size of 100 information bits and code rate r=1/2 the latency would be 162 cycles. The main idea in having a shared hardware structure was to basically map the trellis structure of the smaller Viterbi configuration over the larger one, thereby not taking any extra hardware of its own. The significance would be a reduced complexity of various Viterbi decoders existing on a single shared hardware. 2010 Thesis http://eprints.utm.my/id/eprint/12722/ http://eprints.utm.my/id/eprint/12722/1/MohamedFaridNoorMFKE2010.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Noor Batcha, Mohamed Farid Implementation of reconfigurable viterbi decoders in hardware
description	Channel coders are widely used in digital transmissions where data can be corrupted due to interference. They are used in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital television broadcast, compact disc, and magnetic disk reading. Viterbi decoder is one of the most widely used channel decoders that are used for decoding data that are encoded using convolutional forward error correction codes. This research investigates an adaptive channel coder that is able to switch between few configurations depending on the channel conditions. Channel codes consist of encoders and decoders, and since encoders are rather simple, the main focus of the research is towards the decoders. The research explores into an optimized shared hardware structure between various Viterbi decoders especially of those being used in current technologies such as General Packet Radio Service (GPRS), Enhanced Data rates for GSM Evolution (EDGE), and Worldwide Interoperability for Microwave Access (Wimax). The research looks into optimized methods of memory management and is also aimed for high throughput to be used for high speed applications that are a trend for new and upcoming technologies. Initially the performance of various configuration of Viterbi decoder with respect to different channel conditions was looked into to select few suitable Viterbi decoders to be implemented on Field Programmable Gate Array (FPGA). The final implementation on FPGA combines three Viterbi decoders into a single core. The gain in area of the three Viterbi existing separately when compared to the joint hardware is about 15 %, with no loss in processing speed and throughput. The latency is measured to be a minimum amount with respect to the data size. For a packet size of 100 information bits and code rate r=1/2 the latency would be 162 cycles. The main idea in having a shared hardware structure was to basically map the trellis structure of the smaller Viterbi configuration over the larger one, thereby not taking any extra hardware of its own. The significance would be a reduced complexity of various Viterbi decoders existing on a single shared hardware.
format	Thesis
qualification_level	Master's degree
author	Noor Batcha, Mohamed Farid
author_facet	Noor Batcha, Mohamed Farid
author_sort	Noor Batcha, Mohamed Farid
title	Implementation of reconfigurable viterbi decoders in hardware
title_short	Implementation of reconfigurable viterbi decoders in hardware
title_full	Implementation of reconfigurable viterbi decoders in hardware
title_fullStr	Implementation of reconfigurable viterbi decoders in hardware
title_full_unstemmed	Implementation of reconfigurable viterbi decoders in hardware
title_sort	implementation of reconfigurable viterbi decoders in hardware
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2010
url	http://eprints.utm.my/id/eprint/12722/1/MohamedFaridNoorMFKE2010.pdf
_version_	1747814951967260672

Implementation of reconfigurable viterbi decoders in hardware

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